搜索资源列表
cyc3_ciii51001
- 英文的，给出了Altera公司FPGA器件CIII的基本介绍，相信会有帮助！-English is given FPGA device Altera Corporation CIII basic introduction, I believe will be helpful!
rf_wxtx
- 详细阐述了基于FPGA的RF无线通信技术的原理及硬件设计. 从系统的角度提出RF无线通信的完整设计方案,给出了基于Cyclone II芯片的Nios II的RF无线通信模块框图. 实验结果表明,采用ALTERA的Cyclone II芯片设计实现RF无线通信具有明显优势.-Detailed FPGA-based RF wireless communication technology theory and hardware design. From a system point of view p
led_zfsj
- 现场可编程门阵列( FPGA) 是一种可编程逻辑器件, 它具有丰富的I/O 口及内部资源, 编程和修改极为方便, 并且易于扩展和维护, 简化电子电路的设计。本系统采用Altera 公司的FLEX10K作为核心器件, 结合VHDL程序, 实现了对LED 点阵显示字符的控制。-Field programmable gate array (FPGA) is a programmable logic device, which has a wealth of I/O port and internal
wp_wimax
- WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and t
alterafkex
- fpga design altera flex notes
AlteraFPGA-based-PCI-bus-speed-to-download-the-con
- 基于PCI总线的Altera FPGA高速下载配置设计方案-Altera FPGA-based PCI bus speed to download the configuration design
Altera-Glossary
- 讲述Altera FPGA的术语，挺有用的手册-About the terms of the Altera FPGA, quite useless manual
Design-of-LDPC-codes-on-FPGA
- 小论文《基于FPGA的（3,6）LDPC码并行译码器设计与实现》实现了码率为1/2，帧长为1008bits的规则（3,6）LDPC码译码器-Design and Implementation of Parallel Architectures Decoder for（3,6）LDPC Codes Based on FPGA code rate of 1/2 and block length of 1008 bits has been implemented based on FPGA(S
PS2Keyboard_EN
- document VHDL for keyboard FPGA: Xilinx, Altera
Pradeep-N
- PCIE between altera DSP and FPGA
software-radio-based-on-SOPC
- 介绍了软件无线电的概念和结构， 针对传统软件无线电实现方案， 提出一种基于SOPC 技术的中频软件无线电解决方案。系统采用基于Nios II 软核处理器的SOPC 技术， 在ALTERA 公司 的FPGA 上实现了片上系统。基于SOPC 技术的软件无线电系统具有极高的灵活性、可扩展性，这充分 体现了软件无线电的设计思想。-Describes the software radio concept and structure of traditional software radio i
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
DB4CE15
- Altera公司出品的FPGA IV cyclone DB4CE15核心板的电路原理图 -Altera' s FPGA IV cyclone DB4CE15 produced core plate circuit schematics
ug_cordic
- cordic算法文档,适用于altera的FPGA-cordic docment
数字滤波器的MATLAB与FPGA实现：Altera Verilog版
- 数字滤波器的MATLAB与FPGA实现：Altera Verilog版
锁相环技术原理及FPGA实现 Altera Verilog版
- 锁相环技术原理及FPGA实现 Altera Verilog版