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cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
FPGAEthernetVerilog
- 使用Verilog语言在FPGA平台上控制Ethernet上数据的发送与接收-FPGA realization using Verilog to control transmitting and receiving data over Ethernet
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
564-784-fpga-1-develop
- 该文档主要针对Verilog语言的快速应用指南，包括语法、综合及硬件方面的应用等内容-The document aimed at the rapid application of Verilog language guide, including grammar, comprehensive and content of the application of hardware
latch
- Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b
convolution
- convolution codes using verilog language for FPGA
zhongzhilvbo
- 中值滤波的ＦＰＧＡ（Verilog语言）实现方法，可以作为通信，图像专业的编程参考， -Median filter FPGA (Verilog language) implementation can be used as communication, professional programming reference image,
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
FPGAjiangyi
- 北理工的fpga讲义，不好找，适合verilog学习者-North Institute fpga handouts, easy to find, for verilog learners
Verilog VGA显示 W字形
- 利用VGA显示一个W字形 下载到FPGA来连接显示器使用
VGA全驱动
- 里面有关于FPGA设计的VGA的相应实验说明，以及相关代码
HuaWei-Verilog-
- 华为内部FPGA约束技巧，约束规范，适合新手入门-Huawei within the FPGA constraint techniques, constraint specification, suitable for beginners
coding-style
- 华为FPGA Verilog代码风格，代码规范，适合新手入门-Huawei FPGA Verilog coding style, standardized code, suitable for beginners
DCC2010-FPGA-CPU16ASM-DCC
- cpu verilog 16 bits to control radio software
FpgaFskDemod
- 程序实现一种FSK的解调，语言为verilog。(Program to achieve a FSK demodulation, the language is verilog.)
《HELLO FPGA》-Verilog的关键问题解惑
- 《HELLO FPGA》-Verilog的关键问题解惑,解决Verilog学习过程中的一些问题。
数字滤波器的MATLAB与FPGA实现：Altera Verilog版
- 数字滤波器的MATLAB与FPGA实现：Altera Verilog版
锁相环技术原理及FPGA实现 Altera Verilog版
- 锁相环技术原理及FPGA实现 Altera Verilog版