搜索资源列表
iic_master
- it is a iic source verilog code with its testcase which can act only as master
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
Verilog-CAN-controler
- verilog hdl 语 言 实 现 的 CAN 控 制 器-CAN controller verilog hdl language
Verilog-HDL
- verilog HDL程序入门，很好学，基本和C语言一样，几天就可以简单的编程-verilog HDL program entry, very good school, Basic and C language, a few days can be a simple programming
zhongzhilvbo
- 中值滤波的ＦＰＧＡ（Verilog语言）实现方法，可以作为通信，图像专业的编程参考， -Median filter FPGA (Verilog language) implementation can be used as communication, professional programming reference image,
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
dw_apb_rtc_db
- verilog实现rtc文档，可用于实现RTC。-verilog realize rtc document can be used to implement the RTC.
dw_apb_timers_db
- verilog实现timer参考文档，可用于实现timer。-verilog achieve timer reference documentation can be used to implement the timer.
dw_apb_wdt_db
- verilog实现watchdog参考文档，可用于实现watchdog。-verilog realize watchdog reference documentation can be used to implement the watchdog.
CAM2006
- Verilog allows you to design your digital design at various abstraction levels.Suppose you have an algorithm to be implemented in the form of a digital circuit then you can easily use Verilog constructs to do the same without worrying about the unde
verilog
- Verilogd的设计练习进阶书籍，可帮助开发人员熟练掌握编程 -Verilogd advanced design practice books, can help developers familiar with programming