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二进制串行-1计数器
- 大学计算机数字逻辑实验作业 用Multisim仿真软件编写 计数器 用双D触发器74Ls74构成四位二进制串行计数器 二分频计数原理-University computer digital logic operations using Multisim experimental simulation software used to prepare counter-D Trigger 74Ls74 constitute four serial binary frequency counter t
2分集CDMA跳频通信子程序
- 二分集CDMA跳频通信子程序,计算2分集CDMA跳频通信系统的误码率-two set points CDMA frequency-hopping communications subroutine to calculate two set points Hopping CDMA communication system BER
FPGA_fenpin
- 分频器 FPGＡ程序设计 二分频 对硬件设计有很大用处 -Divider FPGA design process for two minutes frequency hardware design, very useful
VERIOGCLK
- 作clk_in 的二分频clk_out，要求输出与上例的输出正好反相。编写测试模块， 给出仿真波形。-clk_in for the two-frequency clk_out, output and demand were on the output is reverse. Test preparation module, simulation waveforms are given.
fenpin
- 好的分频器设计程序，有三个，二分频，八分频随便改，比较实用
vhdlxdh
- 带同步复位信号的二分频VHDL 程序-synchronous reset signal with the two-frequency VHDL procedures
v
- Verilog写的二分频电路代码，FPGA，实现将输入时钟信号的频率变成原来的1/2-Write Verilog code for the second divider circuit, FPGA, to achieve the frequency of the input clock signal into the original 1/2
erfenpin
- 二分频的实现 二分频的作用是将测相范围由0°~180°扩大到0°~360°。-Two sub-band implementation of the two is the role of sub-frequency measurement phase will range from 0 ° ~ 180 ° extended to 0 ° ~ 360 °.
code
- 用dff方法实现二分频，行为描述实现二分频，二分频，投票代码，有限状态机-Dff method used to achieve two-way, behavioral descr iptions to achieve two-way, two-way, voting codes, finite state machine
clkdiv
- 初学者一个比较容易入门的FPGA verilog 二分频实验。-Relatively easy for beginners to get into a FPGA verilog two-way experiment.
f_test
- tsten通过对clk二分频，实现一秒钟的门脉冲，使被测频率通过，在这一秒钟内，通过计数器计数，实现频率的测定。-tsten half by clk frequency, achieving a second gate pulse to the measured frequency is, at this very moment, through the counter counts, the determination of frequency.
clock_VHDL
- 主要供学习FPGA的人员学习如何写VHDL程序之用，该程序实现了时钟的二分频等功能。-Primarily for learning FPGA-VHDL program to learn how to write use, the program achieved the second clock frequency and so on.
fenpin
- 分频电路的研究 主要包括：偶数分频（二分频、偶数分频占空比50 ）、奇数分频（占空比50 、占空比非50 ）、半整数分频（不要求占空比）、小数分频（不要求占空比）。 -Frequency of the circuit includes: an even frequency (half frequency, frequency 50 duty cycle even), odd-frequency (50 duty cycle, duty cycle of non-50 ), half-
digital-clock
- 数字钟是计时仪器，它的功能大家都很熟悉。本实验对设计的电子钟要求为： 1．能够对s(秒)、min(分)和h(小时)进行计时，每日按24h计时制； 2．min和h位能够调整； 3．设计要求使用自顶向下的设计方法。 数字钟的功能实际上是对s信号计数。实验板上可提供2Hz的时钟，二分频后可产生s时钟。数字钟结构上可分为两个部分c计数器和显示器。计数器又可分为s计数器、min计数器和h计数器。s计数器和min计数器由6进制和10进制计数器构成，小时计数器较复杂，需要设计一个24(或12)
progrm
- FPGA二分频代码，可实现分频器的功能，用于频率的分频-FPGA binary frequency code, the function can be realized divider for frequency division
DIV2
- 二分频，占空比，50比50，VHDL语言-Second, frequency, duty cycle, 50 to 50, VHDL language
clkdiv
- 一个二分频的verilog代码-A divide-the verilog code
Verilog_devided
- Verilog HDL的分频器设计:二分频、三分频和奇分频 -Verilog HDL: the frequency is divided-by-2/3 or others
VGA
- vhdl实现VGA接口显示四种图案：横彩条、竖彩条、棋盘格、白屏。文件包含四个模块：clk_div2——二分频（输入50Mhz输出25Mhz）、makecolor产生彩条信号、vgasyn产生行同步hs和列同步vs、行计数器hadddr、列计数器vaddr，vga_main主程序连接前三个模块。-vhdl implementation VGA interface displays four patterns: horizontal color bar, vertical color bars,
half_clk
- 将clk信号进行二分频，输出频率为其一半的信号-divide