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even_division
- 任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.
Clock_Dividers_Made_Easy
- 用verilog实现任意分频 包含可综合和不可综合代码-Arbitrary frequency with verilog contain comprehensive and non-integrated code
div_n
- verilog占空比50奇偶任意 奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
divFrequencyverilog
- verilog写的任意分频的实现代码，可根据需要配置使用-divide verilog write any implementation code, based on the need to configure
div_any
- 任意整数N分频器的verilog代码，N需要代码中进行设置-Any integer N divider verilog code N need to code set
Odd-Frequence-Dividing-Circuit
- 一种奇数分频电路的设计方法，采用verilog HDL描述。修改代码中参数可以进行任意奇数分频，包含了设计文档和源代码。-A design of odd frequence dividing circuit is presented, which is described by verilog HDL。Change the parameter in code, one can get any odd numbers of frequence dividing circuit.
clk_generator
- 基于Verilog HDL的任意分频代码，由本人原创，可实现0.000001Hz的步进，跟网络上的大部分简单地分频不一样！-Devicetor descr ipted by Verilog，can reach 0.0000001Hz！
fen-pin-Verilog(2013-06-25-09.54.41)
- 任意小数分频，适用于对精确度要求不高的代码中-Any fractional divider, suitable for less demanding precision code
ex1_clkdiv
- Verilog语言编写，通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)