D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots

verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted

Emacs 配置文件，包括自动提示，yasnippet和PHP-mod和cscope等，UNIX系统解压放到HOME目录下就可以，WINDows放到C:\Users\×××\AppData\Roaming下或者你设置的EMACS目录。windows下cscope和cedet可能没法用。-Emacs configuration file, including automatic prompts, yasnippet and other PHP-mod and cscope, UNIX system