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aes
- AES Core Modules In this document I describe components designated to encoding and decoding using AES. aes enc — parametrizable component which can encrypt input data, using 128, 192 and 256 bit key, • aes dec — parametrizable component
aes_inv_cipher_top
- aes ip core, 128 bits
aes
- 基于DM642的AES加密算法 很核心的～-DM642-based AES encryption algorithm is the core ~
aes_crypto_core_latest.tar
- Consecutive AES core Descr iption of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
AES-Administration-and-Maintenance-Guide-Release-
- Implementing a telephony-enabled application using Avaya Telephony Services Application Programming Interface (TSAPI) requires an understanding of TSAPI core concepts of Session and Event Management, control services, and private data. This tutoria
aes_core.tar
- 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
aes-core
- Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
AES-sopc--ip
- 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.
base-on-FPGA-AES-addkey-design
- 介绍了用FPGA实现AES算法所用的开发工具，开发语言和所选用的芯片，及AES算法的硬件实现方式。着重阐述了AES算法FPGA实现的总体设计框图，并副有部分源代码- introduce design tool,language and core of AES which base on FPGA,and AES hardware design.
AES-IP-core-key-expansion-module
- AES IP核密钥扩展模块设计与仿真（设计过程及程序，测试程序）-AES IP core key expansion module design and simulation (the design process and procedures, test procedures)
AES--IP-core-architecture-design
- AES算法分析及其IP核体系结构设计（包括设计过程及代码）-AES algorithm analysis and its IP core architecture design
AES-IP-core-encryption-module-design
- AES IP核加密模块的设计与仿真(包括设计过程及代码)- the AES IP core encryption module design and simulation
AES-IP-core-control-module-design
- AES IP核的控制模块的设计与仿真以及系统集成与仿真-AES IP core design and simulation of the control module and system integration and simulation
core
- aes java实现的文件图片等功能加密，供大家学习使用！-aes java implementation file pictures encryption for everyone to learn to use!
aes_pipe_latest.tar
- Using aes pipeling we improve the speed and throughput of the aes core architecture.
aes
- AES的IP核,AES的加密解密算法，包括密钥扩展程序-aes core verilog
aes-core-include-testbentch
- aes core的verilog代码，包含测试代码和波形文件-aes core verilog code including testbentch
A-compact-AES-core-with-on-line-error-detection-f
- This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logi
AES-File-EnDecryptor-Writed-by-CSharp-master
- 使用 C# 编写的AEC文件加密核心代码源码。(Use C# to write the AEC file encryption core code source code.)