搜索资源列表
CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
ahb_interface.rar
- AHB BUS, Master Slave Arbiter -- example,AHB BUS, Master Slave Arbiter
AMBA-AHB-APB-BUS
- 常见ARM架构的AMBA、AHB、APB总线的介绍，对ARM的总线有个清晰的了解，对各模块的关系也可深入了解-Common ARM architecture AMBA, AHB, APB bus introduction of ARM' s have a clear understanding of the bus, on the relationship between the modules can also be in-depth understanding of
amba
- doc file on AMBA...advanced microcontroller bus architecture ...basic og amba ahb, asb, apb
AMBA_V2.0_CN
- ARM公司高级微控制器总线体系（Advanced Microcontroller Bus Architecture AMBA ）规范中文版，包括ASB，AHB，APB总线-Senior ARM microcontroller bus system (Advanced Microcontroller Bus Architecture AMBA) specification, including the ASB, AHB, APB bus
masterdecoder
- AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
ahb_system_generator_latest.tar
- this project relates ahb
IHI0011A_AMBA_SPEC
- AMBA2.0规范. 研究和开发AHB总线相关的ASIC工程师可以参考-AMBA2.0 specifications. AHB bus-related research and development engineers can refer to the ASIC
AHB_SRRAM
- SSRAM with AHB bus interface source code
AHB
- 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
slaveAHB
- amba总线的AHB部分，与从机相连接口的写法，载自其它网页。-amba AHB bus parts from the machine connected to the interface with the wording set out from other pages.
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
AHB
- AMBA片内总线结构的设计，给需要的人啊。-AMBA on-chip bus architecture is designed to need ah.
AHB
- 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
AHB-BUS-AND-SLAVE-CODE-USING-VERILOG
- AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
AHB_slave-ram
- AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
AHB-Default-Slave-Module
- AMBA2.0版本AHB总线缺省从设备设计方面的技术支持，参考ARM公司AMBA技术手册。对AHB缺省从设备电路的接口、基本逻辑等方面进行介绍。-AMBA2.0 version of the default from the AHB bus support equipment design, ARM AMBA technology reference manual. Default on the AHB slave interface circuit, the basic logic, etc.
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
ahb
- verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)