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dffwewe
- 自己刚编写的vhdl语言来实现的D触发器，自我感觉还可以，也通过了编译，如果有需要就下载去看看吧-just prepared their own language to achieve vhdl D flip-flop, but also a sense of self, but also through a compiler, If there is a need to look at the downloaded Look here
vhdl
- 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
Programming
- 异步置位复位D触发器，基于VHDL硬件描述语言的仿真。-Set asynchronous reset D flip-flop, based on the VHDL hardware descr iption language simulation.
DCHUFAQI
- 一个典型的时序元件D触发器的VHDL描述,希望对大家有帮助-A typical time-series components of the VHDL descr iption of D flip-flop
DtoJK
- Using an edge triggered D flip-flop to implement a JK flip-flop
srandDflipflop
- this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
zonggongcheng
- 三个结合起来的D触发器的vhdl，分别是电平触发，上升沿出发和下降沿出发。-Combining the three D flip-flop vhdl, respectively, trigger level, rising and falling edge start start.
D
- 利用时钟信号实现同步D触发器的功能的vhdl代码-Using D flip-flop clock signal to synchronize the function of vhdl code
D_flip
- source vhdl code of D flipflop logic
D
- 这是一个用VHDL实现一个D触发器的程序-This is a VHDL implementation of a D flip-flop process
vhdl_codes
- D-flip flop vhdl implement code
fli
- --- vhdl code of d flip flop ---- vhdl code of d flip flop ---
VHDL-simple-examples
- 上传的几个VHDL程序：分别是各种功能计数器；使用列举类型的状态机，四D触发器，通用寄存器，伪随机比特发生器，简单的状态机。-Upload several VHDL program: are the various functions of the counter using the enumerated type state machine, four D flip-flop, the general-purpose registers, pseudo-random bit generato
VHDL-book3
- D_flipflop：1位D触发器的设计 D_fllipflop_behav：4位D触发器的设计 reg1bit：1位寄存器设计 reg4bit：4位寄存器设计 shiftreg4：一般移位寄存器的设计 ring_shiftreg4：环型移位寄存器的设计 debounce4：消抖电路的设计 clock_pulse：时钟脉冲电路的设计 count3bit_gate：3位计数器的设计 count3bit_behav：3位计数器的设计 mo
vhdl
- library ieee use ieee.std_logic_1164.all entity decoder is port (clk:in std_logic clr:in std_logic data_in:in std_logic --待解码信元输入端； data_out:out std_logic) --解码信元输出端； end decoder architecture behave of decoder is component dff2
D-trigger
- FPGA/CPLD开发，基于VHDL语言的D触发器的实现-FPGA/CPLD development, based on VHDL implementation of the D flip-flop
D-trigger
- FPGA EPM1270 VHDL D触发器。完整文件夹包-FPGA EPM1270 VHDL D flip-flop. Complete document wallets
D-FLIP-FLOP
- vhdl programme of d flip flop
project.map
- D Flip Flop for Single Bit Store