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lc2
- this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 mode
ep1c6q240sch
- EP1C6Q240 very useful for designer
Oscillograph
- 在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.
reset
- 异步复位同步释放的复位信号处理逻辑代码.Verilog编写!很好用.在EP1C6Q240上调试成功.
svpwm_full_nios
- 这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240
ARM9对FPGA EP1C6Q240进行配置
- 在LINUX下使用ARM9对FPGA EP1C6Q240进行配置的例子,其它FPGA也可参考此代码进行配置
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
ep1c6q240
- Altera公司EP1C6Q240开发板电路图，绝对可用。经试验通过。和大家共享-Altera Corporation EP1C6Q240 development board schematics, is absolutely available. Adopted by the pilot. And for all to share
EP1C6Q240C6
- EP1C6Q240C6开发板原理图，Altera公司的Cyclone系列FPGA—EP1C6Q240-EP1C6Q240C6 development board schematics, Altera' s Cyclone series FPGA-EP1C6Q240
EP1C6Q240-8REG_WR
- altera公司的FPGA的一些开发用的VHDL的源代码用于学习-altera INC. develop fpga vhdl source for study and research
ira_1
- 基于EP1C6Q240 FPGA 核心板的 红外 发射 接收 扩展板 的PCB SCH 的设计文档，红外发射采用PT2248芯片 完成，调制方式 PCM，红外接收采用接收一体头 完成送 FPGA 解码 后 在扩展板的 数码管模块上显示相应内容-EP1C6Q240 FPGA board based on the core of infrared transmitting and receiving expansion board PCB SCH design documents, infrared
launch
- 基于EP1C6Q240 FPGA 核心板的 红外 发射 接收 扩展板 的PCB SCH 的设计文档，红外发射采用PT2248芯片 完成，调制方式 PCM，红外接收采用接收一体头 完成送 FPGA 解码 后 在扩展板的 数码管模块上显示相应内容-EP1C6Q240 FPGA board based on the core of infrared transmitting and receiving expansion board PCB SCH design documents, infrared
Twister_DDR_SDRAM_Board_Manual
- Twister DDR EP1C6Q240 FPGA 开发板 原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
music
- 乐曲硬件演奏电路设计 由顶层文件和数控分频、乐曲简谱码对应的分频预置数查表电路、8位二进制计数器（ROM的地址发生器）组成。演奏乐曲“梁祝”，乐曲可改。已经过硬件下载测试（使用芯片EP1C6Q240 Cyclone系列）-Music by the top hardware performance circuit design file and the NC frequency, music notation code number corresponding to the preset fr
cyclone
- 在LINUX下使用ARM9对FPGA EP1C6Q240进行配置的例子,其它FPGA也可参考此代码进行配置.-Use the ARM9 in LINUX configuration of FPGA EP1C6Q240 example, other FPGA code can refer to this configuration.
pin-defination
- 使用tcl文件分配管脚 比如在quartus里面建立一个setup.tcl的tcl文件，器件为EP1C6Q240 第3，4行表示所有不用的管脚默认为输入三态 第6，7行分别把芯片的28和2脚分配给了设计中的clk和key1 -Use of tcl quartus such as file allocation pins inside a setup.tcl the tcl file, the device is EP1C6Q240 3,4 line that all un
AD
- 基于EP1C6Q240的AD转换代码，新手易懂-The AD converter based EP1C6Q240 code, novice to understand
counter
- 基于EP1C6Q240的计数器设置，简单易懂，调试通过-Counter EP1C6Q240 based settings, easy to understand, debug through
DA
- 基于EP1C6Q240的DA转换程序代码，简单易懂，调试通过，基于quartus 6.0-The DA conversion based EP1C6Q240 code, easy to understand, debug through, based on quartus 6.0
FREQ
- 基于EP1C6Q240的频率计设计，简单易懂，调试通过，基于quartus6.0-Based on the frequency meter EP1C6Q240 design, easy to understand, debug through, based on quartus6.0