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用Verilog hdl实现i2c总线功能
- 用Verilog hdl实现i2c总线功能，对i2c总线有很大帮助-with Verilog hdl i2c bus function of i2c bus is very helpful
i2c总线控制器 Xilinx提供
- 用Verilog hdl实现i2c总线功能，对i2c总线有很大帮助-i2c bus contrll functions implemented by Verilog hdl.
i2c(FPGA)
- 基于FPGA的i2c总线模拟，采用verilog hdl语言编写。-FPGA-based i2c bus simulation, using verilog hdl language.
i2c
- 用verilog hdl实现i2c Master Controller 的设计，包括主程序设计和测试程序设计-Verilog hdl using i2c Master Controller to achieve the design, including the main program design and test program design
i2c
- 标准i2c读写时序，verilog hdl-Standard i2c read and write timing, verilog hdl
Veriloghdl_code
- 几个常用的接口实验的程序代码，用Verilog hdl语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、i2c、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog hdl language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, i2c, marquees
i2c19861208888
- i2c总线模拟，verilog hdl编写的总线模拟控制程序-i2c bus simulation, verilog hdl prepared bus analog control procedures
i2c.tar
- i2c verilog hdl code including test environment
i2cVerilog
- i2c 控制器的 Verilog源程序, 适用于FPGA等应用领域-i2c controller Verilog source code,i2c controller Verilog source code
i2_cmaster
- verilog hdl i2c主机代码-verilog hdl i2c host code
i2c
- i2c主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备i2c通信能力 模块由Verilog hdl编写 并经Cyclone II FPGA测试-i2c master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII i2c communication capability . This mo
i2c_verilog
- verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
i2c
- verilog hdl file i2c interfacing-verilog hdl file i2c interfacing
i2c.tar
- i2c core for verilog hdl
i2c
- 文档是用Verilog hdl写的i2c源代码，是很不错的一个技术文档。-The document is written in Verilog hdl i2c source code, is a very good technical documentation.
i2c
- 本源代码中用Verilog hdl语言编写了i2c的顶层及子模块文件，详细完整，并在Altera实验板上得以验证-primitive code discribe the i2c s function using the Verilog hdl language, the code are particular and integrity,moreover it has been validated in the altera FPGA and passed
i2c
- 语言：verilog 功能：用Verilog hdl编写的i2c主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language:
i2c
- i2c的Verilog hdl简单学习程序-The Verilog hdl simple i2c learning process
i2c
- 基于hdl的i2c开发学习资料，仅供参考，但是对初学者有用。-Based on the the hdl i2c development learning materials for reference only, but is useful for beginners.
i2c-slave
- verilog hdl i2c协议从机的编写-verilog i2c protocol from the machine