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用Verilog HDL实现I2C总线功能
- 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
I2C总线控制器 Xilinx提供
- 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
i2c(FPGA)
- 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
I2C
- 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
i2c
- 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl
VerilogHDL_code
- 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees
I2C19861208888
- i2c总线模拟，verilog hdl编写的总线模拟控制程序-i2c bus simulation, verilog hdl prepared bus analog control procedures
i2c.tar
- I2C verilog HDL code including test environment
I2CVerilog
- I2C 控制器的 Verilog源程序, 适用于FPGA等应用领域-I2C controller Verilog source code,I2C controller Verilog source code
i2_cmaster
- verilog HDL i2c主机代码-verilog HDL i2c host code
I2C
- I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This mo
i2c_verilog
- verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
i2c
- verilog hdl file i2c interfacing-verilog hdl file i2c interfacing
i2c.tar
- i2c core for verilog hdl
I2C
- 文档是用Verilog hdl写的I2C源代码，是很不错的一个技术文档。-The document is written in Verilog hdl I2C source code, is a very good technical documentation.
I2C
- 本源代码中用Verilog HDL语言编写了I2C的顶层及子模块文件，详细完整，并在Altera实验板上得以验证-primitive code discribe the I2C s function using the Verilog HDL language, the code are particular and integrity,moreover it has been validated in the altera FPGA and passed
I2C
- 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language:
I2C
- I2C的Verilog HDL简单学习程序-The Verilog HDL simple I2C learning process
I2C
- 基于hdl的i2c开发学习资料，仅供参考，但是对初学者有用。-Based on the the hdl i2c development learning materials for reference only, but is useful for beginners.
i2c-slave
- verilog HDL i2c协议从机的编写-verilog i2c protocol from the machine