搜索资源列表
PCICOREGUIDE
- 本指南讲述支持的基于 Virtex™ 和 Spartan™ 架构的 32 位和 64 位核的设计流程，并且介绍 Cadence® IUS v5.8 中的示例设计。-This guide based on the support of the Virtex ™ and Spartan ™ architecture 32-bit and 64-core design process, and Cadence ® IUS v5.8 intr
MichaelJackson.ZIP
- Michael jackson nauiobfisuabsiubfisuabuifbsuifbsif ius buiaf
AMSD_in_GUI.tar
- 锁相环（pll）AMS仿真实例，平台为cadence+ius。-tutorial for the simulation of mixed signal pll
review-paper-aradhana
- this ius a research paper on ofdm mimo systems
i2c_testbench
- i2c verilog rtl with testbench very good code and works perfectly with cadence ius and ncverilog
42,0426,0010,EN
- fronius froni us fron ius fron nius