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quartusII_clock
- vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
QuartusII6.0_ppt
- QuartusII6.0的英文培训资料277页的ppt宝贵资料，图文并茂，一步步教你使用Quartus
multi-wave-creator
- 基于FPGA的多波形发生器（编程环境QuartusII6.0）
clock
- 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。 使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。
SCI
- VHDL写的SCI接口。quartusII6.0的工程！
QuartusII6[1].0shiyong
- Quartus 视频教程 短短不到十分钟学会Quaruts-A short video tutorial Quartus less than 10 minutes Quaruts Society
NiosII_clock
- 用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
ps2_keyboard
- FPGA PS2键盘驱动设计，使用软件QuartusII6.0 verilog-FPGA PS2 keyboard-driven design, the use of software QuartusII6.0 verilog
dds
- 使用VHDL硬件描述语言实现了直接频率合成器的制作，并在Altera公司的CycloneII上得到实现，验证了代码的正确性。用户操作可以参照程序中的说明，请使用QuartusII6.0以上版本打开，低版本打开时会有错误提示-Using VHDL hardware descr iption language to achieve a direct frequency synthesizer production, and Altera s CycloneII be realized, to ver
rom
- 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
sram64
- 随机存储器VHDL代码，已用quartusII6.0验证，可用，可实现模块-Random access memory VHDL code has been used to verify quartusII6.0 can be used to deliver modules
butterfly
- 另一种蝶形运算的代码，可用quartusII6.0运用-A butterfly operation of the code, the use of available quartusII6.0
LCD1602Display
- FPGA中LCD1602驱动开发设计，软件quartusII6.0，verilog-LCD1602 driver in the development of FPGA design, software quartusII6.0, verilog
QuartusII6.0
- 是QuartusII6.0使用步骤视频，很实用，很方便，用时不多但效率高-Is the use of steps QuartusII6.0 video, very practical, very convenient to use, when a small but efficient
QuartusII6.0_cn
- QuartusII6.0简体中文教程.pdf，讲的很详细，共有260页，很好的资料-QuartusII6.0 English tutorial. Pdf, said very detailed, 260 pages, very good information
QuartusII6.0
- eda实验\EDA技术实验指导书new eda实验\EDA技术实验指导书new -eda new
FPGAandRS232-485VerilogSourcecode
- FPGA串行通信口RS232-485构建，RS232和485有选择控制，源程序基于QuartusII6.0用Verilog语言撰写。-FPGA serial communication port RS232-485 build, RS232 and 485 to selectively control, source-based QuartusII6.0 written in Verilog language.
eda
- 本实验目标是利用FPGA逻辑资源，编程设计实现一个串行通用异步收发器。实验器件为“创新综合实验平台”上集成的Altera NIOSII开发板，FPGA芯片型号为EP1C12F324C8。电路设计采用VHDL硬件描述语言编程实现，开发软件为QuartusII6.0。-The goal is to use the FPGA logic resources, programming design realize a serial general asynchronous transceiver. Th
FPGA-chuankoutongxin
- 本文详细介绍了串行通用异步收发器设计原理及调试方法同时还介绍了QuartusII6.0软件的应用，此外还介绍了FPGA实现接口电路设计-This paper introduces the general asynchronous serial transceiver design principle and the debugging method is also introduced QuartusII6.0 software application, in addition, it also