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mipssingelcycle
- mips single cycle implementation five files auxiliary pc data memory instruction memory adder forwarding
singlecycle_mips
- single cycle mips design by verilog.
singleCycleProc
- 简化的单时钟循环VHDL处理器.可以运行一些简单的mips指令，例如add, sub, and, or, slt, beq and j. -A simplified single cycle processor in VHDL. This processor can continuously execute some simple MIPS instructions which are lw, sw, add, sub, and, or, slt, beq and j.
F10-Single-Cycle-MIPS
- This a verilog code of single cycle mips-This is a verilog code of single cycle mips
mips
- 利用Verilog HDL硬件描述语言实现单周期MIPS_CPU设计。-Design of single-cycle MIPS_CPU
project3
- mips single cycle cpu
MIPS
- 用VHDL设计单周期的MIPS处理器,实现简单的指令-VHDL design with single-cycle MIPS processor, simple instructions
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
single_cycle
- single cycle mips code in vhdl
MIPS-processor-Verilog-code
- 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instruct
mips--cpu
- 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic de
SCMIPS
- 使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
Lab7
- CSCE2214课程设计，试验7源代码。实现单周期的MIPS CPU 16位。-CSCE2214 curriculum design, test 7 source code. Achieve single-cycle MIPS CPU 16 place.
scmips_cpu
- 自己写的单周期mips CPU和测试工程-Write your own single cycle mips CPU and test engineering
mips
- mips单周期支持add、sub(包括无符号、立即数)、跳转指令-mips single-cycle support add, sub (including unsigned immediate value), the jump instruction
mips
- 基于MIPS架构实现的单周期处理器，包含多种基本操作，验证方法是把自己的学号写进连续内存。-MIPS-based architecture for single-cycle processor, includes a variety of basic operations, authentication method is to learn their numbers written contiguous memory.
mips
- 一个单周期流水CPU的实现，其中mips4.vhd是顶层文件-A single cycle CPU
FinalProject_16854131_code
- VHDL single cycle mips processor-single cycle mips processor
mips
- implement of mips data path in single cycle with vhdl language
single
- 单周期MIPS处理器的设计，附带测试文件。(The design of a single cycle MIPS processor comes with test files.)