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  1. wb_lpc_latest.tar.gz

    1下载:
  2. Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
  3. 所属分类:Communication-Mobile

    • 发布日期:2017-03-29
    • 文件大小:401.32kb
    • 提供者:Arun
  1. flash

    1下载:
  2. fpga的FLASH读写VERILOG代码。希望对大家有用-the verilog code of fpga read/write flash
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2016-01-24
    • 文件大小:928byte
    • 提供者:Denny
  1. ram

    0下载:
  2. 存储器模块生成,采用16位数据总线,5位读写地址总线,异步清零!-Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:2.29kb
    • 提供者:齐磊
  1. pci_t

    0下载:
  2. verilog开发的PCI target模块,能完成配置空间的读写以及单次的memory读写,原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:10.19kb
    • 提供者:齐培红
  1. r_w_flash

    0下载:
  2. FPGA高速完成AD采集回来的数据进行高速读写FLASH存储-AD Acquisition completion of FPGA high-speed data back to high-speed read and write FLASH memory
  3. 所属分类:Embeded-SCM Develop

    • 发布日期:2017-03-31
    • 文件大小:880.05kb
    • 提供者:王瓶
  1. rom

    1下载:
  2. 只读存储器VHDL代码,可运行实现,已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:1.29kb
    • 提供者:干璐
  1. readandwrite

    1下载:
  2. 三星k9系列flash memory读写程序-K9 Series Samsung flash memory to read and write procedures
  3. 所属分类:FlashMX/Flex

    • 发布日期:2016-12-01
    • 文件大小:1.53kb
    • 提供者:晓婕
  1. cpu16

    0下载:
  2. 实现一个16位CPU。该CPU使用精减指令集,是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
  3. 所属分类:Windows Develop

    • 发布日期:2017-03-29
    • 文件大小:6.06kb
    • 提供者:周健
  1. jtag

    1下载:
  2. JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter. This package has open and modular architecture with ability to write miscellaneous extensions (like b
  3. 所属分类:Windows Kernel

    • 发布日期:2015-03-25
    • 文件大小:935.35kb
    • 提供者:asdf
  1. sram

    0下载:
  2. to write and read from an sram. its actually a logic cell,when the write enable is high its possible to write data onto a memory location when read enable is high we can read the data in given memory location
  3. 所属分类:Other systems

    • 发布日期:2017-04-03
    • 文件大小:36.78kb
    • 提供者:mariamma
  1. LPC2DDR2

    0下载:
  2. Module Function Descr iption: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:8.49kb
    • 提供者:吴羽中
  1. ddr2_controller

    0下载:
  2. DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-26
    • 文件大小:50.93kb
    • 提供者:yanxp
  1. OneNAND_in_embed_sys

    1下载:
  2. OneNAND闪存在嵌入式系统中的应用 OneNAND Flash是三星公司开发的一类Flash芯片,它克服了传统NAND Flash接口复杂的缺点,具有接口简单、读写速度快、容量大、寿命长、成本低等优点。文章从软硬件两方面介绍了其在嵌入式系统中的应用,特别是逻辑块和物理块地址的映射、读写擦操作、坏块处理、性能优化等技术。-OneNAND flash memory in embedded system applications developed by Samsung' s OneNA
  3. 所属分类:software engineering

    • 发布日期:2016-11-30
    • 文件大小:46.61kb
    • 提供者:zhangdong
  1. led_control

    0下载:
  2. 本实验箱采用的液晶显示屏内置的控制器为SED1520,点阵为122×32,需要两片SED1520组成,由E1,E2分别选通,以控制显示屏的左右两半屏。图形液晶显示模块有两种连接方式,一种为直接访问方式,一种为间接访问方式。本实验采用直接控制方式。 直接控制方式就是将液晶显示模块的接口作为存储器或I/O设备直接挂在计算机总线上。计算机通过地址译码器控制E1和E2的选通;读/写操作信号R/W有地址线A1 控制,命令/数据寄存器选择信号由地址线A0控制。 -The experimenta
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.15mb
    • 提供者:yangxiao
  1. cpu

    0下载:
  2. 设计以及基本的CPU,至少包括四个基本单元,控制单元,内部寄存器,ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its perf
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-10
    • 文件大小:2.09mb
    • 提供者:mollyma
  1. xapp944_source

    0下载:
  2. 主要用来实现FPGA控制nand flash存储器的读写控制,是公司网站提供-FPGA is mainly used to achieve control of read and write nand flash memory control, is the company website
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:1.09mb
    • 提供者:lijin
  1. Audio_Reader_Flash_DE2

    0下载:
  2. This an DE2 card software, which is able to read some Audio file from a memory (Flash for example). Extendable to read from a SD card, and to write on it.-This is an DE2 card software, which is able to read some Audio file from a memory (Flash for
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:74.93kb
    • 提供者:Minimus
  1. CCD

    1下载:
  2. 本设计主要用来进行图像采集处理,通过摄像头采集图像信息,经过插值算法后存储到外部SDRAM,然后读取图像数据,进行边缘滤波处理后经VGA输出到屏幕上。-This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and th
  3. 所属分类:Video Capture

    • 发布日期:2017-03-29
    • 文件大小:12.06kb
    • 提供者:申永帅
  1. CPU-Project

    0下载:
  2. CPU设计,包含基本的指令集,能执行简单的程序。考虑了CPU,寄存器,存储器和指令集之间的关系。即读写寄存器,读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-13
    • 文件大小:3.23mb
    • 提供者:ilmf
  1. nansflash

    0下载:
  2. NANDFlash存储器作为一类非易失性存储器,具有功耗低、读写快、容量大、成本低、抗震性好等优点而被广泛应用于各种嵌入式系统。 - The NANDFlash memory takes a kind of nonvolatile storage, has the power loss to be low, the read-write is quick, the capacity is big, the cost is low, the anti-knocking property go
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-14
    • 文件大小:3.4mb
    • 提供者:刘颖
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