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Phase_Locked_Loop
- 对一般的PLL及APLL,定点PLL进行了MATLAB SIMULINK仿真，可以由程序直接生成PLL的VHDL和C源代码
ver-fir-coefficient
- vhdl source,ver-fir-coefficient,simulink of fir with soft ware input
DSPBuilderreferencemanual
- DSP Builder 参考手册,主要用于simulink实现算法后，可将其自动转换为vhdl语言应用。-DSP Builder Reference Manual, mainly for simulink algorithm may be automatically converted to VHDL language applications.
FSKxinhaochafenxitong
- FSK差分检波系统仿真的课程设计 本课程设计主要利用MATLAB集成环境下的Simulink仿真平台，设计一个FSK信号差分检波系统。观察FSK调制前后的信号波形,并对调制前后信号的频谱进行分析,再以调制信号为输入，构建差分检波解调系统电路，观察解调前后的信号波形，并对解调前后信号的频谱进行分析。加入噪声分析通过三种不同信道FSK信号差分检波系统接受信号的性能。仿真结果，基本达到课程设计要求。-FSK differential detection system simulation of
MyState
- 这份是实验课上的教师和学生用的实例。关于用matlab simulink仿真状态机并生成vhdl代码的详细内容-The experimental class teachers and students to use examples. Matlab simulink simulation on the use of state machine and generates VHDL code details
oqpsk
- OQPSK的matlab/simulink仿真程序,程序中在基带仿真了oqpsk的调制方式-OQPSK of matlab/simulink simulation program, the program in the base-band simulation of the modulation OQPSK
matlab_to_vhdlfpga
- 本文提出了加快发展之路 从理论设计,通过Matlab / Simulink环境 在定点算法对其行为模拟的 在FPGA或定制实现硅片。这个了 实现了netlist移植的Simulink系统 描述成的硬件描述语言[VHDL]。在这个例子中,这个 Simulink-to-VHDL转换器被设计来使用 代码来描述结构VHDL系统互连, 允许简单的行为说明基本模块。 结果VHDL bit-true交付后代码 比较定点Simu
DES
- DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
2fsk-2psk
- 基于CPLD的数字通信系统 2fsk-2psk 用VHDL产生 2fsk-2psk信号-CPLD-based digital communications system 2fsk-2psk generated by VHDL signals 2fsk-2psk
73462697msk_matlab
- 于毕业设计与论文以及做课题用-MSK Simulink simulation program for the design and graduation thesis topic, and making use -Design and graduation thesis, as well as issues to do with-MSK Simulink simulation program -于毕业设计与论文以及做课题用-MSK Simulink simulation program for
89346497fpga-example2
- 于毕业设计与论文以及做课题用-MSK Simulink simulation program for the design and graduation thesis topic, and making use -Design and graduation thesis, as well as issues to do with-MSK Simulink simulation program -于毕业设计与论文以及做课题用-MSK Simulink simulation program for
sysgen_gs
- Xilinx system generator的上手指南，system generator用于在matlab中使用simulink设计硬件，很方便-guide of system generater by Xilinx
usetheModelSimtosimulink
- 详细介绍了如何使用ModelSim进行仿真.-it will teach you how to use the ModelSim to simulink.
CDMACoax
- this a mix file.in this cdma vhdl ,simulink file included-this is a mix file.in this cdma vhdl ,simulink file included
cic
- 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC，解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
Simulink-to-VHDL-Route
- This paper presents the way of speeding up the route from the oretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting
3813412-Matlab-Simulink-Simulink-Matlab-to-Vhdl.r
- Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms
simulink-matlab-to-vhdl
- convert matlab and simulink files to vhdl
DDS
- 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
count
- VHDL file contains the project data code for final project