搜索资源列表
VHDL--testbench
- VHDL 的testbench 编写风格及技巧，有助利用modelsim做仿真，一看就会！-The testbench VHDL writing style and skills will help make using modelsim simulation, a look will be!
8051单片机源码verilog版本
- 8051单片机源码verilog版本 包括rtl， testbench， synthesis ,Verilog source code version of 8051, including rtl, testbench, synthesis
testbench
- 关于如何写Verilog测试台的文档，对于测试程序很有帮助噢-On how to write Verilog test documents, test procedures for helpful Oh
VHDL38decoder
- VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序-38 decoder VHDL language implementation, including program source code file, there are testbench test procedures
vhdltestbench
- testbench,VHDL的，适合初学者使用-testbench
testbench
- how to write testbench,use vhdl-how to write testbench, use vhdl
testbench
- 这是讲述如何编写testbench的，我认为很经典的。值得一看-This is how to prepare Testbench, I think is very classic. Worth a visit
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
testbench
- ritting testbench 入门级的还有XILINX的一篇文档how to write a testbench。 你看看这个，看思想。-entry-level ritting testbench are XILINX a document how to write a testbench. You take a look at this, look at the ideological.
RAMtestbench
- 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
risc
- 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
adder4
- 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
spi2-testbench
- test bench for spi communication
generic_testbench
- VHDL中关于generic的用法，及其testbench，可以使用Modelsim仿真查看其功能-the usage of generic,a testbench file is given, we can use it to simulate the generic s function
TestBench
- 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_log
uart-vhdl-testbench
- simple uart vhdl behavioural model (package) vhdl testbench example
testbench
- vhdl modelsim testbench examples-vhdl modelsim testbench for modelsim with vhdl examples
testbench
- 详细介绍了在vhdl语言仿真中怎么编写测试平台代码.-introduce how to write testbench in VHDL
testbench
- 介绍了fpga设计中，利用testbench设计源码测试激励文件，很方便很详细-Introduced fpga design, test stimulus using testbench design source files, it is more convenient
VHDL--TESTBENCH
- VHDL描述的TESTBENCH写法 ,对新人有帮助。-The use of VHDL to write TESTBENCH files.useful for new people