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ddc
- 随着数模转换器硬件的快速发展和DSP处理能力及处理速度的逐步提高，软件无线电技术在商用和军用无线电通信领域也越来越显示出其强大的吸引力。本文研究的高速中频采样和数字下变频技术是目前蓬勃发展的软件无线电领域的两项关键技术。-As advances in technology provide increasingly faster and less expensive digital hardware, more of the traditionally analog functions of a
verilog
- 本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the inter
cordic_atan
- 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。 鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated usin
quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y
bpsk
- 基于能量检测的频谱感知.由于实际信道中的多径和阴影效应，单个认知用户频谱感知的性能受到影响，因此需要靠不同用户间的协同频谱感知来对抗多径和阴影效应。本设计要求在文中采用一种协作机制，即两用户进行协作频谱感知，提高主用户的检测率，减少检测时间，并且得到捷变增益。要求给出仿真结果。-spectrum sensing in cognitive radio based on energy detection.As the channels in diameter and shadow, not a si
ddc
- 电子科大2009-应用于无线电监测的高速信号处理平台设计，软件无线电的DDC的FPGA实现！-UESTC 2009- applies to wireless monitoring of high-speed signal processing platform design, software radio DDC' s FPGA implementation!
usrp_inband_usb_WORKS
- 通用软件无线电平台的FPGA代码，非常有用。用Verilog编写-Universal Software Radio Platform FPGA code, very useful. Written by Verilog
complete
- 用Verilog编写的数字钟与汽车尾灯模块。其中数字钟具有时间显示的基本功能，按键校时校分，闹钟模块（包含校时校分），仿电台报时（四低一高），整点报时，12-24显示切换等强大功能。-With a digital clock in Verilog modules and automotive taillights. Digital clock which displays the basic functions of a time, school hours when school keys,
energy_sensing
- 认知无线电中频谱检测算法采用能量检测实现，verilog编写的，只有.v文件，需要自己综合编译-Cognitive radio frequency spectrum detection algorithm uses energy detection to achieve, verilog prepared only. V file, needs its own comprehensive compilation
PC-CFR
- 采用matlab simulink编写的消峰参考设计，可以直接生成verilog代码。消峰主要用于降低无线信号的峰均比，提高功放效率。-Clipping prepared using matlab simulink reference design, you can generate verilog code directly. Consumers peak mainly used to reduce radio signal PAR, improve power amplifier effic
DCC2010-FPGA-CPU16ASM-DCC
- cpu verilog 16 bits to control radio software
homedb
- 射频卡协议，射频识别，RFID（Radio Frequency Identification）技术，又称无线射频识别，是一种通信技术，可通过无线电讯号识别特定目标并读写相关数据，而无需识别系统与特定目标之间建立机械或光学接触。(Radio frequency identification, RFID (Radio Frequency Identification) technology, also known as radio frequency identification, is a kin