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verilog-clock
- 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Verilog(clock)
- 用VERILOG语言编写的电子钟程序.是用GW48教学实验箱仿真
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
clock
- 用verilog语言实现数字时钟，有注释，规范-Digital clock using verilog language, there are notes, specifications
Verilog
- verilog digital clock
clock
- verilog 实现的跑表程序。可以对这个程序加以修改，可是显现电子钟的设计。设计可以根据需要实现分秒。同时可以改成是LED的跑等程序。功能强大的很！-verilog implementation stopwatch program. This procedure can be modified, but the show clock designs. Design can be according to the need to achieve every second. At the same
15NIOSIIclock
- nios num clock verilog code
clock
- 实现时钟的计时、报时功能，verilog实现。-To achieve time clock, timekeeping functions, verilog achieve.
clock
- 本实验实现一个能显示小时，分钟，秒的数字时钟（贝一特电子）Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
timer
- 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
clock
- 用verilog实现的数字跑表，下载到FPGA开发板上验证通过。下载后从新分配引脚即可用。-Verilog implementation using digital stopwatch, download to FPGA development board to verify the adoption. After the download you can use the new distribution of pins.
paobiao
- 一个用verilog编的时钟程序A clock with the procedures for verilog-A clock with verilog program for A clock with the procedures for verilog
verilog
- 多功能数字时钟的verilog语言描述，基于quarters II平台-Multifunction digital clock verilog language descr iption of quarters II-based platforms
clock
- simple clock over verilog
spi
- SPI Verilog code with programmable clock
clock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
verilog
- verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signal
clock
- verilog hdl代码 实现显示在数码管上显示时间，日期-verilog hdl code to achieve control in the digital display shows time, date. .
clock
- verilog数字钟 Verilog HDL 写的不是很好,有好的就不要下我的了-verilog clock
Clock generator
- A clock Generator in verilog