搜索资源列表
rs-codec-8-16
- 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
rs-codec(255-223)
- 这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。-This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.
rs-codec-8-4
- encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplic
曼彻斯特编解码Verilog代码
- 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
1553_enc_dec.rar
- 1553B编解码程序 verilog 描述,1553B codec procedures described in verilog
H.264
- 详尽地论述了H.264 特点、编码器原理、解码器原理、编解码器的实现。为了更好地理解H.264 编解码原理及其实现，第7 章详细介绍了H.264 码流的句法和语义。最后对H.264 视频编码传输的QoS 进行了专门地论述。-H.264 are discussed in detail the characteristics of the principle of encoders, decoders principle, the realization of codec. To better un
JPEG2000
- jpeg 2000 encoder complete document
Wolfson-WM8731-audio-CODEC
- audio codec data sheet
tx
- 关于通信原理课程设计中HDB3编解码的一个VERILOG源代码-Principles of curriculum design on the communications HDB3 codec in a Verilog source code
madplay-0.16.1b
- 经典的C语言MP3编码解码实现,可以在linux/unix平台下编译运行. -Classic C language realize MP3 codec, you can linux/unix platform running under the compiler.
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
D_BLAST44
- MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
manchester_verilog
- 用verilog写的一个manchester code的代码，含编解码-Used to write a verilog code for manchester code containing codec
rs-codec(255-223)
- RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。-RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.
RS_Verilog
- rs编解码的verilog实现源代码，从硬件实现rs的编解码-rs codec to achieve the verilog source code, from the hardware codec rs
2
- RFID系统的IEEE的文章，安全协议，认证- In this paper, we first propose a cryptographic authentication protocol which meets the privacy protection for tag bearers, and then a digital Codec for RFID tag is designed based on the protocol. The protocol w
DE2_70_AUDIO
- 是用VERILOG HDL和NIOS II C/C++ 编的DE2-70板子的音频编解码芯片的使用工程-Is VERILOG HDL and NIOS II C/C++ code of the DE2-70 board in the audio codec chip, the use of project
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, d
NEW AUDIO CODEC DEVELOPMENT CODE BASE
- Hi friends, This consists of a complete system written in Verilog/TCL for VGA DISPLAY OF RESULTS INPUTTED THROUGH AUDIO CODEC AND COMPLETE SYSTEM LEVEL DESIGN ON VERILOG.