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pingpufx
- 本设计以凌阳16位单片机SPCE061A为核心控制器件,配合xilinx virtex-ii FPGA及xilinx公司提供的硬件DSP高级设计工具System Generator,制作完成本数字式外差频谱分析仪。前端利用高性能A/D对被测信号进行采集,利用FPGA高速、并行的处理特点,在FPGA内部完成数字混频,数字滤波等DSP算法。
virtex_ii_Pro_LINUX
- 在xilinx virtex-ii Pro Development Board开发板上移植LINUX系统-Porting MontaVista Linux to the XUP virtex-ii Pro Development Board
xilinxisdisclosingthisSpecification
- xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”,概述 Texas Instruments EMIF。 ? 第 2 章“virtex-ii 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000 EMIF 连接到 virtex?-ii 系列或 Spartan?-3 FPGA 的实现。 ? 第 3 章“virtex-4 FPGA 到 EMIF 的设计” 描述将 TI TMS320C6
xilinx
- xilinx可编程逻辑器件的高级应用与设计技巧 全面介绍xilinx的CoolRunnerii Spartan-3 virtex-ii virtexii pro等器件的结构特性,以及ISE6及其辅助设计工具。 -xilinx programmable logic devices and design techniques for advanced applications a comprehensive introduction to xilinx s CoolRunnerii Sparta
ddr_sdr_V1_1
- DDR控制器 - 用xilinx virtex ii FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in xilinx virtex ii FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted
Advanced-xilinx-FPGA
- Advanced xilinx FPGA Design with ISE Objectives Describe virtex™ -ii advanced architectural features and how they can be used to improve performance • Create and integrate cores into your design flow using the CORE Generator™
DesignandFPGAImplementationof
- In most cases, a bandpass filter characteristic is obtained by using a lowpass-to-bandpass frequency transformation on a known lowpass transfer function. This frequency transformation controls the location of passband edges and transfer zero
xilinx_question
- :ISE5.1i是xilinx推出的具有ASIC-strength的设计工具,它充分发掘了virtexⅡPro系列芯片的潜力;virtex-ii Pro 系列芯片的密度是从40,000门到8,000,000门。同4.1i相比,设计人员在编译时所花的时间得到了成倍提高(从100,000/min增加到200,000门/min)并且在器件速度上增加了40 。-: ISE5.1i is a xilinx introduced a ASIC-strength design tools, which ful
GeneratingFPGA-AcceleratedDFTLibraries
- 关于DFT的文章,应用FPGA实现傅立叶变换。-Abstract—We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT). The partitioning strategy is a heuristic based on the DFT
virtex2_Manual
- xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with xilinx hardware devices. You may not reproduce, distribute, republish, downlo
qpsk_demod_use_FPGA
- 根据软件无线电的思想,提出了一种新颖的数字信号处理算法,对QPSK信号的相位进行数字化处理,从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差,用数字锁相实现收发端载波的同步,在频偏较大的情况下,估算频偏的大小,自适应设置环路的带宽,实现较短的捕获时间和较好的信噪性能。整个设计基于xilinx公司的ISE开发平台,并用virtex-ii系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点,符合未来通信技术发展的方向。-According
FPGA-FFT-design
- FPGA 实现高速 FFT 处理器的设计 介绍了采用 xilinx 公司的 virtex- ii 系列 FPGA 设计高速 FFT 处理器的实现方法及技巧。-FPGA design to achieve high-speed FFT processor implementation methods and techniques in the design of high-speed FFT processor using xilinx virtex-ii FPGA family.
humanpong
- 我们的目标是建立一个人力乒乓球比赛的FPGA板(xilinx公司的virtex-ii Pro的XC2VP30与的Digilent公司VDEC1的视频解码器)。-Our group objective is to build a Human Pong game on an FPGA board (xilinx virtex-ii Pro XC2VP30 with the Digilent VDEC1 Video Decoder).
test_myip
- xilinx EDK virtex ii xc2vp30 用户自定义IP核led灯实验-the xilinx EDK virtex ii xc2vp30 user-defined IP core led light experiment
vga_module
- VGA 显示源码。基于xilinx virtex ii 开发板开发。实现单色显示功能。-VGA display
Asynchronous_FIFO
- 异步FIFO代码,虽然是一个比较简单的程序,但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in virtex-ii FPGAs writen by Peter Alfke. This TechXclusive xilinx website. It has some minor modifications.
Video_filterinf
- Project Report-Real-time User Adjustable Video Filtering create an embedded system that demonstrates real-time video filtering using a xilinx virtex ii multimedia board
Real-time User Adjustable Video Filtering
- Real-time User Adjustable Video Filtering aim is to create an embedded system that demonstrates real-time video filtering using a xilinx virtex ii multimedia board
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in xilinx virtex ii FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe