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fir_finall
- 用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
ActivH71sp1pch_1156042493
- ActivH71sp1pch有关active HDL得.好像.-ActivH71sp1pch HDL in the active. Like.
memory_example
- This simple example allows you to get familiar with Active-HDL s Memory Viewer.
SRAM_Control
- VHDL Code for SRAM Control (Synthesized with Synplify-Pro, Active-HDL Simulation)
2
- RFID系统的IEEE的文章，安全协议，认证- In this paper, we first propose a cryptographic authentication protocol which meets the privacy protection for tag bearers, and then a digital Codec for RFID tag is designed based on the protocol. The protocol w
finalcoursework
- 用VHDL代码写的模拟微处理器核程序，有计算模块和register file 等模块，并包含测试程序，调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL
active-hdl-vhdl-code
- this vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.-this is vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.
counter_4bit_code
- vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares-vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares....
active-hdl
- active_hdl_教程pdf版.ppt.+试验+仿真+入门-active_hdl_ tutorial pdf version
ACTIVEHDL
- In this module we prepare our students to familiar with ACTIVE-HDL TOOLS, which is used for Compilation and Simulation purpose.
VLIB_LE_FE_ZE
- LE, FE and ZE libraries for Active-HDL.
000600_HowtoUseIPCoreGeneratorinActive-HDL
- how to use ipcore in active hdl
xors_1
- this xor gate in vhdl run under active hdl-this is xor gate in vhdl run under active hdl
mux2
- this is multiplexer gate in vhdl run under active hdl
eetop.cn_Active-HDL-9.1crack
- active hdl 仿真vrack-active hdl simulator vrack。。。。。。。。