搜索资源列表
mini_aes
- aes算法的verilog hdl实现，供给大家作为参考 。-Orangk'aes algorithm verilog hdl realized, we supply as a reference.
AES_RTL
- 使用Verilog HDL 實現AES硬體加解密
mini_aes_latest[1].tar
- AES 加解密 代码, 有文档说明，testbench-AES encoding decoding source code in HDL
comp1
- 实现了加密狗的功能，完成此功能用的硬件描述语言，verilog hdl 在各方面是最好的，欢迎下载。-fpga aes
AES
- 利用verilog HDL实现的AES算法，在密码芯片加解密中显示出了突出的优越性-The reference-AES.V which has been uploaded is particularly useful for researchers who are dedicated to the password-chip researching.
verilog-for-AES-algorithm
- 介绍了verilog HDL语言对AES算法进行数据加解密。-Introduced the verilog HDL language to AES algorithm for data encryption and decryption.
sbox
- It is AES sbox implementation with verilog HDL/ it is most recently made and works well. Very easy to understand please doen load enjoy!
tiny_aes_latest.tar
- 主要实现使用verilog HDL语言实现AES的加密算法-Main implementation using verilog HDL language implementation of AES encryption algorithm
AES
- AES加解密Verilog HDL源代码，具体的算法参照相关书籍，里面含有testbench-AES encryption and decryption Verilog HDL source code, reference books specific algorithm, which contains testbench
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
AES
- 这是一个AES加密算法的程序，适用verilog hdl语言写的-A AES ALGORITHM
aes-master
- aes master by vhdl code and decode
aes128-hdl-master
- Verilog AES hdl key 128 bit code and decode
aes-project-master
- aes project vhdl FPGA