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aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
高级加密算法
- AES加密和解密源码！-AES encryption and decryption source!
RIJNDAEL_DE_TOP
- AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
AES_verilog
- AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
cunzip
- AES CODE FOR DECRYPTION
aes_decrypt
- This the Top Module for AES Decryption algorithm-This is the Top Module for AES Decryption algorithm
test_dec1
- This Module creates the test Bench for AES Decryption Algorithm
FPGA_128_AES_decryption
- 以FPGA具體實現的128-bit AES decryption，包括介紹文件以及源碼。-FPGA-based 128-bit AES decryption
decryption
- AES decryption in VHDL!! Wit LCD controls
avs_aes_latest.tar
- AES algorithm decryption Encryption
AESvhdl
- AES vhdl, encryption, decryption code
Advanced-Encryption-Standard-(AES)
- AES decryption standards, vhdl code
aes_imp
- AES CODE IN VHDL FOR ENCRYPTION AND DECRYPTION
aes
- 此程序完成aes的硬件语言实现部分，通过vhdl语言完成加解密过程。-This process is complete aes hardware language section, vhdl language to complete the encryption and decryption process.
AES-Encryption-VHDL-master
- AES Encryprtion an decryption algorithm
AES-FPGA
- 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA
Coding Files
- We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely