搜索资源列表
ahb2ahb.rar
- AMBA总线AHB TO AHB bridge,AMBA bus AHB TO AHB bridge
tb_ahb_master.rar
- this is a AMBA AHB code for master.,this is a AMBA AHB code for master.
CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
AHBtoAPB.rar
- amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc,amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
ahb_interface.rar
- AHB BUS, Master Slave Arbiter -- example,AHB BUS, Master Slave Arbiter
dma_ahb_latest.tar
- this shows the ip code for dma controller of amba ahb in vhdl.
ahb_ram
- AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such
AMBA-AHB-APB-BUS
- 常见ARM架构的AMBA、AHB、APB总线的介绍，对ARM的总线有个清晰的了解，对各模块的关系也可深入了解-Common ARM architecture AMBA, AHB, APB bus introduction of ARM' s have a clear understanding of the bus, on the relationship between the modules can also be in-depth understanding of
appnote65_quickmips_ahb_interface_design_example.r
- appnote65_quickmips_ahb_interface_design_example AHB接口设计-appnote65_quickmips_ahb_interface_design_exampleAHB Interface Design
DW_8b10b_enc.v.tar
- amba ahb protocol with test benches
ahb2wishbone_latest.tar
- opencore ahb to wishbone bus verilog code
amba
- doc file on AMBA...advanced microcontroller bus architecture ...basic og amba ahb, asb, apb
camera_up
- Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境
AHB
- 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
AHB
- 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
AHB-BUS-AND-SLAVE-CODE-USING-VERILOG
- AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
ahb
- verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
AHB-task-slave-master
- ahb master行为级模型，ahb slave模型(AHB master behavior level model, AHB slave model)