搜索资源列表
apb.rar
- APB master verilog code,APB master verilog code
APB
- It s the verilog source code for AMBA APB 2.0 Slave
a_vhdl_8253_timer_latest.tar
- 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
apb2ahb
- verilog code for apb to ahb convert
RTC
- verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等-verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other
au
- 基于APB总线的uart控制器，包括源码和vcs脚本-UART controller based on AMBA APB
LIP1701CORE_system_watchdog
- System watchdog verilog code
I2C
- iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现-iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation
ahb2apb
- Verilog实现的AHB2APB bridge代码-Verilog code to achieve the AHB2APB bridge
Ahb2Apb
- AHB总线协议转APB总线协议的接口IP，使用Verilog代码实现，有详细的英文注释(AHB bus protocol turn APB bus interface IP, use Verilog code implementation, and have a detailed knowledge of the English comments)
apb.v
- AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
apb
- APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
apb
- Verilog code for APB Protocol
apb_timer
- Verilog code of timer for APB
Desktop
- apb sourc code in verilog
apbtoaes128_latest.tar
- verilog实现的AES加解密程序，接口为APB总线。(AES encryption and decryption program implemented by Verilog)
apb-uart
- apb—uart模块，实现中断处理和异步收发数据并处理(APB - UART module, interrupting processing and asynchronous receiving and receiving data and processing)
apb_uart
- 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
24_Timer
- 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
apb_timer.tar
- 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the descr