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使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
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This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
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用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
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convolution is important and is widely used in digital signal processing.For example, in LTI system.
Input two sequences of 8-bit 2 s complement signed numbers with length 2~8. the input values range is -128~127.
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VHDL code for convolution encoder for wimax PHY layer. This design also has control to add controlled amount of noise in encoded output.
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卷积码（213）的编译码，VHDL语言编写的整个工程文件，带有仿真结果图。-Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.
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