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FFT_64point
- 该工程实现了一个64点DIF FFT，verilog编写，通过Modelsim功能仿真。
fft64.rar
- 采用verilog代码编写了一个64位的fft，其中蝶形算法采用基2算法,the fft of 64 points
64point_FFT
- 64-point Pipeline FFT，包含Verilog语言编写的64点FFT运算rtl级程序以及测试程序，此外，还包含设计文档。-64-point Pipeline FFT, Verilog language includes a 64 point FFT computation rtl-level procedures and testing procedures, in addition, includes the design documents.
64R4SDFpoint_FFT
- 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
FFT8
- FFT8，8点FFT运算，用verilog vhdl 语言编写，可以应用于64点FFT-FFT8, 8 点 FFT computation, using verilog vhdl language, can be applied to 64-point FFT
64point_FFT
- 64点FFT代码 基4算法 Verilog-64-point FFT code radix-4 algorithm Verilog
fft64
- verilog hdl 编写的64点fft代码，适合很多芯片-coded by verilog hdl that implement 64 point fft, suite to many core
FFT_64points
- 64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。-64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.
verilog-radix4
- Master Thesis(FFT_RADIX-4)-This thesis deals with a 64-point Radix-4 in-place FFT, based on an improved FFT algorithm. The whole FFT structure was implemented based on self-designed modules and by manipulating the embedded Virtex II FPGA’s module
TTLV-Nguyen-Vu-Quang
- THIS document was written by verilog code. It s content talkes about descr iption 64 FFT
pipelined_fft_64
- FFT 64-point by verilog code
pipelined_fft_64_128_256
- 用verilog实现64点，128点，256点的fft(64 points, 128 points, and 256 points FFT are implemented with Verilog)