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vhdl0716
- ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。
uart
- ARN7核s3c44b0串口程序源码,包括FIFO,非FIFO多模式的接收发送.
UART.使用FPGA的FIFO，状态机
- 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。,The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
UART_spec
- a UART model with FIFO buffer, design with verilog
Uart(FIFOSend.TimeoutReceive)
- AVR mega16/mega32的UART FIFO发送.超时接收,广泛应用于工业控制.这是原创作品.-AVR mega16/mega32 send the UART FIFO. Overtime receiver is widely used in industrial control. This is the original works.
int_uart8051
- UART realization for at89c5131 with FIFO and interrupts.
UART
- A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the
FIFOSRC
- DSP uart窗口通信中的一种通信格式，FIFO模式的一个小程序-dsp serial communication uart communication first in first out-FIFO mode
FIFO-UART
- 基于ARM7-LM3S1138的FIFO方式的UART数据传输代码-ARM7-LM3S1138 based on the FIFO mode of UART data transmission code
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
uart
- 此文档为C51单片机串口通讯学习程序（中断+FIFO)-This document is for the C51 microcontroller serial communication learning process (interrupted+ FIFO)
uart
- Also the USART automatically senses the start of transmission of RX line and then inputs the whole byte and when it has the byte it informs you(CPU) to read that data from one of its registers. The USART of AVR is very versatile and can be setup
fifouart_latest.tar
- vhdl fifo uart core datasheet
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
UART
- 基于FPGA的UART设计，包含接收模块，发送模块，FIFO模块-UART FPGA-based design, including the receiver module, sending module, FIFO module
fifo
- VHDL 带FIFO的 UART 求大神帮忙修改-VHDL with FIFO UART pursuing big God help modify
s3c2440---UART
- s3c2440de UART用法，用s3c2440来实现非FIFO的UART通信-s3c2440de UART usage to achieve non-FIFO UART communication with s3c2440
uart
- 基于Libero11.3平台的带收发FIFO的UART程序-Based Libero11.3 platform with the FIFO UART transceiver program
uart
- 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
fifo
- 一个简单的FIFO实现，基于STM32的UART+DMA方式。(A simple FIFO implementation, based on the STM32 UART+DMA approach.)