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spitoi2s3
- spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
an-032904-codec
- I2S fpga interface ip design from xe-I2S fpga interface ip design from xess
i2s interface
- i2s interface VHDL language FPGA. Using for MEMS microfone
I2S_IF
- GV7601 I2S FPGA实现的功能-GV7601 I2S RTL
i2s_input
- 基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真-FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment
i2s_top
- i2s接口fpga实现，工作在主模式，ISE和vivado下已验证(I2S interface FPGA implementation, working in the master mode)
i2s_interface_latest.tar
- i2s 接口的vhdl实现，可用于FPGA(i2s interface with VHDL)
i2s_interface
- verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)