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I2C_IPcore_VHDL
- 这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核，可直接编译运行-I2C serial data communication protocol to VHDL hardware descr iption language of the IP core can be directly translated Operation
I2c Core IP 核
- 可在SOPC中运行的IP核，经过系统验证
oc_i2c_master.rar
- I2C core,经过验证可以在SOPC上运行的IP核,I2C core, verified SOPC can run on IP nuclear
I2C_IP_core
- I2C IP CORE 及开发文档, 网上搜集-I2C IP CORE and the development of documentation, on-line collection of
I2C
- 详细描述了I2C的技术规范 版本号为2.1 是采用VHDL编写I2C的IP核的一本不错的参考资料-A detailed descr iption of the I2C specification version 2.1 is the use of VHDL for the preparation of the IP core I2C a good reference
I2C
- IIC通信协议IP核，描述IIC协议在FPGA上的实现-IIC communications protocol IP core
1
- 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
i2c_master_slave_core
- I2C master/slave IP core
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
components
- quartus的几个IP核（PWM,RAM,I2C）-quartus several IP core (PWM, RAM, I2C)
freedev_i2c
- FREEDEV数字应用开发板上的I2C总线IP核的verilog描述-FREEDEV digital application development board I2C bus IP core verilog descr iption of
I2CSLAVE
- 已经验证过的I2C，slave的IP，core，从一开源网站下载的，代码写的非常好，节省了FPGA的资源，比起以往的slave的CORE，这个CORE减少了寄存器的使用。-Has been verified I2C, slave of the IP, core, from an open source website, the code is written in a very good save FPGA resources than the previous slave of CORE, t
I2C_code
- 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
i2c_latest.tar_1
- I2C的OPEN CORE 的代码，很使用，可以直接改参数-I2C open core ip。verilog
i2c
- I2C IP CORE Verilog quartus-I2C IP CORE Verilog quartusii
I2C
- 本文件是在quartus II环境下编译的，功能为I2c控制模块。可作为IP核使用！-This document is compiled in quartus II environment, the function I2c control module. Can be used as IP core to use!
i2c
- I2C master mode IP core
IPCores_iic_8051
- I2C_IP_Core, 使用VHDL 和VERLOG编写，并有文档说明-I2C IP Core, VHDL/Verilog
i2c_core
- i2c ip core support slave and master mode
i2c
- 这是基于altera avalon-MM总线的I2C IP核。利用VHDL语言编写。(This is an I2C IP core based on the altera avalon-MM bus. Using VHDL language.)