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IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE
- IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
xge_mac_latest.tar.gz
- Language - Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. ,Language- Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defin
IEEE_Verilog_2001
- 原版IEEE verilog/VHDL 2001标准。-IEEE verilog/VHDL 2001
IEEE_Verilog_2001
- Verilog 2001 编程规范,作为ASIC和FPGA逻辑开发人员学习不可多得的资料,也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
iir_par_code
- IIR code. IEEE STD 1364-1995 Verilog file: iir_par.v.
IEEE_standard_Verilog_HDL1364_2001
- IEEE standard Verilog HDL1364-2001.pdf Verilog 学习必备资料-IEEE standard Verilog HDL1364-2001.pdfVerilog learning essential information
FPGAREAL
- 信号处理FPGA实现参考,IEEE transaction 的一篇文章。主要针对信号处理中加窗、FFT、VSLI快速实现中误差地等问题。-FPGA realization of a reference signal processing, IEEE transaction of an article. Mainly for signal processing windowing, FFT, VSLI rapid error problems.
Verilog
- 很不错的Verilog 书籍 ,包括ieee标准和黄金指南-Very good Verilog books, including ieee standards and Gold Guide
alu_Verilog
- It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2008)".
2
- RFID系统的IEEE的文章,安全协议,认证- In this paper, we first propose a cryptographic authentication protocol which meets the privacy protection for tag bearers, and then a digital Codec for RFID tag is designed based on the protocol. The protocol w
fpu100_latest.tar
- 这是一个32位的浮点运算单元(FPU),它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
verilog-ieee
- verilog introduction
ofdm
- ofdm调制解调的fpga实现。使用Verilog实现IEEE 802.16a系统的调制解调模块。-ofdm modulation and demodulation of fpga implementation. Verilog implementation using IEEE 802.16a system, modem module.
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
IEEE.Standard.Verilog.Hardware.Description.Languag
- IEEE Standard Verilog Hardware Descr iption Language-IEEE Standard Verilog Hardware Descr iption Language(
emiraga-ieee754-verilog-b7a63aa
- IEEE 754 floating point
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstractio
IEEE Standard for Verilog 2005
- IEEE Standard for Verilog 2005
IEEE Standard for Verilog 2005
- this book introduces the use of Verilog HDL.
IEEE Verilog Standard 1364-2001
- IEEE Verilog Standard 1364-2001.pdf IEEE Verilog-2001标准