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jk触发器
- 基于matlab的jk触发器，已通过运行。
Apache+JK+Tomcat_集群
- Tomcat压力分流 整合 多个tomcat
vhdl
- 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
iis-tomcat-jk
- IIS连Tomcat的改进版。主要是修改了原来手机访问时存在的一些问题。-jk mod enhancement, just remend the problem of mobile access
jk-ff
- j-k flip flop implementation in XCS2-j-k flip flop implementation in XCS200
jkff
- JK flip-flop is implemented using VHDL
jakarta-tomcat-connectors-jk-1.2.6-src.tar
- 用于linux中,tomcat与apache的整合-For linux in, tomcat and apache integration
vhdl_jk
- 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
DtoJK
- Using an edge triggered D flip-flop to implement a JK flip-flop
5
- Code for JK flip flop and SR flip flop
jk
- jk触发器在rs触发器的基础上进行改进，可以将jk=1的输入状态定义为合法状态。-jk flip-flop in the rs flip-flop based on the improvement can be jk = 1 of the input state is defined as the legal state.
trigger
- D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
JK
- Tomcat与Apache或IIS集成的JK插件，并给出了5.0的tomcat及apache服务器，可直接集成使用。集成后，对开发大任务量WebServer程序很有用！-The JK plugin for tomcat intergrating with Apache or IIS. It s useful to develop webserver programe in dealing with high volume task.
JK
- 一个JK触发器 虽然比较简单 但或许会对你有用 里面代码跟仿真都有-FPGA
count10
- 十进制计数器 自己尝试编辑的，可以-jk flip-flop, try to edit their own, using state machine to achieve, you can-Decimal counter his attempt to edit, and can-jk flip-flop, try to edit their own, using state machine to achieve, you can
jk
- 触发器设计范例，JK触发器的VHDL实现-Trigger for example, JK flip-flop of VHDL implementation
03-jk-ff-BCDcounter
- JK-flip flup-BCD counter with proteus
JK
- JK触发器的功能实现，采用VHDL编程，可以下载到FPGA中进行演示-JK flip-flop implementation of function, using VHDL programming, you can download a presentation to the FPGA,