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LTE无线网络仿真平台，涵盖物理层
- LTE无线网络仿真平台，涵盖物理层，mac层，和核心网的主要entity，是最新的比较全面的仿真LTE的工具-LTE simulation platform, including PHY, MAC, core network entity.
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
S2E-TI
- 嵌入式串口转以太网控制器，以下简称S2E21，是一款具有高效性能并集成了ARM Cortex-M3微处理器的串行至以太网控制器。该控制器的核心是高度集成的32位Stellaris LM3S6432 ARM Cortex-M3微处理器，具有50MHz性能和96K快速单周期片上闪存及32K SARAM内存，可高效处理网络流量。Stellaris系列微处理器采用LQFP-100 封装，并集成了片上10/100MB以太网MAC和PHY，从而能够最大限度的节省空间。-Embedded Serial to
usb20_usb11
- usb 2.0 功能模块源代码 usb 1.1 数字物理层源代码-usb 2.0 function core from opencores.org usb 1.1 phy core
usb_latest.tar
- 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
m-mtip-10_100_1000_ethermac
- 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
USB_IP-CORE-design
- USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
RT3050_5x_V2.0_081408_0902
- The RT3052 SOC combines Ralink’s 802.11n draft compliant 2T2R MAC/BBP/RF, a high performance 384MHz MIPS24KEc CPU core, 5-port integrated 10/100 Ethernet switch/PHY, an USB OTG and a Gigabit Ethernet MAC. With the RT3052, there are ver
Ethernet_MAC_10-100-Mbps_latest.tar
- The Ethernet IP Core is a MAC (Media Access Controller). It connects to the Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other. The core has been designed to offer as much flexibility as possible to all kinds of applications
KSZ8342_Data_Sheet
- IP电话专用芯片 The Micrel KSZ8342Q 文档资料。-The Micrel KSZ8342Q Analog Telephone Adapter (ATA) supplies a complete solution for enterprise and residential environments, converting analog signals from a traditional telephone of fax machine for transmission
phy-core
- Generic Phy framework for Linux v2.13.6.
phy-core
- phy-core.c Generic Phy framework. -phy-core.c Generic Phy framework.
dwmac-socfpga
- Overwrite val to GMII if splitter core is enabled. The phymode here is the actual phy mode on phy hardware, but phy interface EMAC core is GMII. -Overwrite val to GMII if splitter core is enabled. The phymode here is the actual phy mode on phy hard
help_lib
- 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core man