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Ddelay
- 在Quartus下使用D触发器来加入延迟，每个D触发器增加半个周期的延迟，稍加更改可以得到不同的延迟。
Altera Quartus II 10.1最新破解文件
- Altera Quartus II 10.1最新破解文件，本人一直独家专用，X86和X64都有。-Altera Quartus II 10.1 latest crack file, I have been exclusively dedicated, X86 and X64 have.
DDS
- 基于quartus的DDS，可以发生正弦波，方波，三角波，附带了顶层文件，注释在程序中-Quartus on the DDS, can occur sine wave, square wave, triangle wave, with the top-level documents, notes in the procedure
FPGA_AD7822
- 基于FPGA的AD转换控制器设计，AD7822，quartus II，verilog hdl-A Design of the A/D Convertion Control Module Based on FPGA
ADC0809
- 用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
usb-blaster
- quartus多种USB-bletera 自制下载线！
Quartus2_cracker_72sp2
- Quartus 7.2工具软件的破解文件， 从中国区总代理处流出。-Quartus 7.2 software tool to break a document from the Department out of the general agent in China.
analogue-digi-ana-converter
- design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an ana
DFFquartus
- D触发器 quartus实现 有RTL图-D flip-flop to achieve a RTL Figure quartus
dtrigger
- 常用触发器——D触发器的VERILOG语言描述，可用Quartus II 9.0 和modelsim环境实现。-Common triggers- D flip-flop of VERILOG language descr iption available Quartus II 9.0 and modelsim environment to achieve
DFF_BDF
- D触发器设计图形输入法,设计软件quartus-Input D flip-flop design graphics, design software quartus
exp1.8_Dflipflop
- 用VHDL及verylog语言设计一个D触发器，可以在Quartus II中仿真-Language Design with VHDL and verylog a D flip-flop, the Quartus II simulation in
exp_micro_s
- 自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。 1.echo uart,接收rx_data,再回复！ 2.运行时请注意完整路径： D:\EXP\EXP_SOPCbuilder\exp_micro_s 3.UART数据输入问题？ 3.1 MODELSIM中w完信号后，run/restart一次。 3.2 设置clock=20ns。 3.3 命令行中输入uart_drive调出uart_
Part4
- RS Latch and D Latch on Quartus
Trigger
- 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
round
- 利用实验箱标配的AD_DA板上的D/A数模转换器，模拟一个圆的波形，学习LPM_ROM（1024*10）宏功能模块的定制与使用，最后利用Quartus II完成设计、仿真。-The the experimental box standard AD_DA panel D/A converters, a round analog waveform, learning LPM_ROM (1024* 10) the megafunctions the customization and use last
dtrigger
- 在Quartus软件中用Verilog HDL编写的D触发器的源代码-In the the Quartus software using the Verilog HDL prepared D flip-flop the source code
D_FF_ok_D
- Learning FPGA students can see, this code USES VHDL language to write D flip-flop, not only can learn QUARTUS software, also can better enhance the digital circuit design.