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this a pack include source code for quartus 2.
It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 mode
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写DPRAM状态机，Quartus -DPRAM write state machine, Quartus II
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读DPRAM状态机，Quartus -DPRAM read state machine, Quartus II
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驱动ADS8365状态机,Quartus II Verilog-Drive ADS8365 state machine, Quartus II Verilog
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用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
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基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
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Quartus II工程压缩文件，是一个典型的基于FPGA的计价器工程项目，有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
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基于quartus的，状态机实现流水灯，verilog HDL语言编写-Quartus-based, the state machine to achieve water lights, verilog HDL language
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Final state machine written on VHDL in Quartus II. Imple. Implements the working principle of a sensor which detect the spinning direction (e.g. a motor) and depending on the direction a DuplexCounter is set to "up" or "down" mode.
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用Altera Quartus II 的VHDL语言完成的状态机控制步进电机的程序员代码-The use of Altera Quartus II VHDL language to complete the state machine code programmer stepper motor control
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Mealy型有限状态机设计，设计软件quartus，有详细注释-Mealy type finite state machine design, design software, quartus, with detailed notes
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Moore型有限状态机设计，设计软件quartus，有详细注释-Moore-type finite state machine design, design software, quartus, with detailed notes
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状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state
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1、用FPGA/CPLD实现HS162字符液晶显示。
2、分析相应的功能要求，分析CPLD与字符液晶HS162的接口典型电路。
3、利用状态机的设计方法，通过指令编程实现对HS162-4液晶模块的读/写操作，以及屏幕和光标的操作。
4、编写模块的Verilog HDL语言的设计程序。
5、在Quartus II软件或其他EDA软件上完成设计和仿真。
-This design of a CPLD-based controls HS162 to achieve character
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通过设计一个简化的计算机模型，培养利用有限状态机的概念设计复杂电路的思维，在设计过程中体会VHDL的RTL风格描述以及EDA工具Quartus的使用方法。同时了解CPU的控制原理与控制过程
通过动脑和动手解决数字逻辑设计中的实际问题，明确，巩固和灵活应用所学的理论知识，提高设计能力和实践操作技能。
-Through the design of a simplified computer models, to cultivate the concept of finite state ma
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简单状态机数码管显示,Quartus II VHDL设计语言-Asimple state machine digital tube display, Quartus II VHDL design language
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finite state machine in verilog use quartus to program it into FPGA
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利用VHDL编写SPI传输与接收协议，发送单字节信息，状态机思想-Use VHDL to write SPI transmission and receiving protocol, send a single-byte information, the state machine
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基于FPGA的状态机程序例程设计。使用的是Mearly型状态机。通过此状态及设计过程来熟悉在Quartus中状态机的设计方法-FPGA based state machine routine design. Using Mearly type state machine. With this status, and the design process to become familiar with the design method in the state machine in Quartu
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流水灯状态机的一段式描述和二段式描述还有三段式描述的Verilog源码-Light water section of the state machine and the two-stage type descr iption descr iption descr iption of Verilog source code as well as three-
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