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sdr_sdram
- 详细的SDRAM控制器HDL代码，最顶层代码，很清晰-detailed SDRAM controller HDL code top-level code, it was very clear
sdr_sdram
- SDRAM顶层模块,大家可以看看，学习一下模块的化分
sdr_sdram
- 很好用的！很好用的代码1SDRAM的源码！一定有用
sdr_sdram
- 文章详细讲述了sdr_sdram控制器的使用和编程思想-sdr_sdram
sdr_verilog
- 用Verilog实现SDR_SDRAM的控制器,可用FPGA实现对普通SDRAM的读写操作!-SDR_SDRAM using Verilog implementation of the controller, the FPGA can be used to achieve the ordinary SDRAM read and write operations!
sdr_sdram
- sdram控制器顶层模块的VHDL源程序文件，可直接用-sdr SDRAM
sdr_sdram
- sdram控制器，verilog语言写的-sdram controller, verilog language to write
SDR_SDRAM_IP
- SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
sdr_sdram
- 用FPGA实现SDRAM的控制，主要是将SDRAM的时序搞懂，这个很好做出来了。-Using FPGA realize SDRAM control, mainly the SDRAM timing out, this is very good do.
SDRAM controller
- This SDRAM controller is useful for SDR_SDRAM IC's can be integrated with the verilog code. The code is developed for the altera FPGA's and it can be ported to other FPGA's easily. The code is verified with terasic DE2-115 board and DE2 boards.
sdr_sdram
- sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)