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shizhong
- 用vhdl语言描述时钟的功能，并通过七段译码显示输出。-VHDL language used to describe the function of the clock and through the Seven-Segment display decoder output.
shizhong
- 简单的VB时钟控件操作，对于刚学习VB.net的人很有帮助-VB simple clock control operation, for people just learning VB.net helpful
shizhong
- 这个VHDL与其他上传的代码不同，这个代码更适合于初学者。电子时钟已经在硬件上得到成功仿真。-From the VHDL code with other different, the code is more suitable for beginners. Electronic clock has been successful in the hardware simulation.
shizhong
- 数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
shizhong
- 时钟程序设计，为用vhdl语言设计编写的电子时钟显示分秒位-Clock programming, vhdl language designed for use in the preparation of accurate digital electronic clock display
shizhong
- 一个用VHDL语言编写的时钟程序，软件平台是Quartus II 7.2 ，它是由前面上传的小模块组合起来制作的，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -A clock with the VHDL language program, the software platf
shizhong
- 用eda 技术实现电子时钟的基本功能,包括定时，跑秒等功能。（这里只有源代码）-This is a simple chengxu write by vhdl
shuziluji
- 纯VHDL文件 拥有闹铃 整点报时 日历 使用方法（打开文件shizhong.gdf文件编译即可（本人使用maxplus-Pure VHDL files have calendar alarm whole hour to use (you can open the file shizhong.gdf file compilation (I use maxplus))
shizhong
- vhdl描述的数字钟，功能一样，方法不同-vhdl descr iption of the digital clock, the same function, different methods
shizhong
- vhdl电子时钟（24小时制，时、分、秒）描述-VHDL electronic clock (24 hours to make, points seconds) descr iption
dian-zhi-shizhong-vhdl-yu-yan-shiji
- 电子时钟VHDL程序与仿真包含了电子时钟设计的全部代码-good good good good good good good good good good good good good good good
shizhong
- VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。-verilog HDL
shizhong
- VHDL时钟芯片设计，走时加显示,用于XC3S50-TQ144，引脚已定义，可直接载入运行-VHDL clock design with display
shizhong
- VHDL硬件语言实现时钟功能（只有分秒），在Quarter 2上的编程。-VHDL hardware language clock function (only minutes and seconds), the programming of the Quarter 2.
shizhong
- 这是用VHDL编写的数字逻辑时钟电路，实现计时和由23:59到00:00转换的功能，已经在FPGA中测试通过！-This is written in VHDL digital logic circuit。It can realize the function of timing and by 23:59 to 00:00 conversion, has been in the FPGA test through!
shizhong
- VHDL设计带报警的59分钟定时器，系统以秒速度递增至59分钟后,启动报警1秒钟,置位后又以秒速度递减至零并报警1秒钟。-VHDL design with alarm 59 minutes timer