搜索资源列表
A Verilog HDL Test Bench Primer
- Lattice公司的A Verilog HDL Test Bench Primer应用手册-Lattice A Verilog HDL Test Bench Primer Handbook
spi2-testbench
- test bench for spi communication
multiplier_8_bit
- This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit)
edge_detection
- edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
santhosh_verilog_adder
- This has code off multibit Adder. IT is written in verilog. The associated test bench for the verilog code is also attatched within the rar file. Uncompress the rar file and the file name describes the function of each code file.. Comments are we
test_bench
- test bench for booth multiplier
fft_gen
- FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho &
sqrt
- This zip file contains the verilog source code for square root calculation and its test bench
FastCplxMuply
- This zip folder contains the verilog code for fast complex multiplication source code and its test bench
logarithm
- - logarithm matlab code, verilog code, test bench - document
Processor_alu
- this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
xge_mac
- 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below.
Verilog_Simulation
- Verilog simulation 如何用verilog写Test bench末进行仿真-Verilog simulation It describe how to write a test bench in veriog for design simulation.
Xilinxtestbenchwriting
- This book is all about test bench writing in verilog and VHDL.
ASIC_VHDL_FPGA_design_lectureNotes
- 这是美国普渡大学（Purdue University West Lafayette)ASIC design 的课件完整版！带事例和讲解的非常好的VHDL学习材料！含有vhdl 基础知识，设计步骤，UART, RTL,Test Bench 以及测试和调试，DEBUG等各种VHDL设计者必学知识！-This is Purdue University (USA) ECE 337 ASIC design class lecture notes! very classic! The content inc
adder_fa4bit
- 4 bit full adder verilog code n test bench
SAP-processor-with-Test-Bench-working
- SAP processor in verilog with test bench complete and working
code
- it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm
VHDL-counter--Test-bench
- Test Bench VHDL Code for Counter
TEST-BENCH.vhd
- test bench for ddr 1