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ULPI_v1_1.rar
- 是UTMI+Low Pin Interface specifacation,适合搞USB驱动的兄弟姐妹.,UTMI+Low Pin Interface specifacation
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
USB2.0
- UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。 -UTMI called USB2.0 Transceiver Macrocell Interfac
ULPI_v1_0Errata
- 是UTMI+Low Pin Interface specifacation的错误更正,适合搞USB驱动的兄弟姐妹.-UTMI+Low Pin Interface specifacation s errata
USB2_UTMI_1_05
- USB2.0标准的UTMI接口，对想了解USB的IP的朋友很有帮助的-USB2.0 UTMI,GOOD DOCUMENT
utmiplus_whitepaper
- UTMI+ for USB application development-UTMI+ for USB application development
UTMI_signal
- usb 2.0 hardware descr iptor-utmi applications
Shared-Digital-Logic-of-UTMI
- THIS PDF MAINLY HAVING THE DOCUMENTATION OF USB UTMI LAYER ..SHARED DIGITAL LOGIC OF PHYSICAL LAYER AND ALSO CODING OF TRANCEIVER BLOCKS
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi
fpga_usb_serial_20131205.tar
- usb serial core is a vhdl synthesizable code, implementing serial data transfer over usb. Combine with a UTMI-compatible transceiver chip, this core acts as a USB device that transfers a byte stream in both directions over the bus
utmi
- 介绍USB PHY接口中的UTMI接口， 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)