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vedicmuliplier
- Vedic multiplier design in Verilog HDL
Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas
- The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture base
mul_barrel
- vedic multiplier. it is a 8x8 multiplier.
pid
- It is a verilog code for a vedic multiplier using a barrel shifter
2.-Novel-High-Speed-Vedic-Mathematics-Multiplier.
- 2. Novel High Speed Vedic Mathematics Multiplier
verilog-code-for-8bit-multiplier-using-vedic-algo
- The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
vedic-multiplier-for-16-bit-input-data
- vedic multiplication is used to implement on FPGA. here the vdic multipler uses urdhwa tiryakhbyam sutra to multiply 16 bit numbers, which is applicable for all data type numbers. This uses vertical and cross wise multiplication process. The out
ved-mul-ut
- About vedic multiplier which uses efficient methodology which reduces the time taken to calculate
8bit_vedic_multiplier_latest.tar
- Hai here i attach 8x8 vedic multiplier source code
6.complex-multiplier-using-vedic
- DemoCodesOutex.m shows the basic operations of CLBP.
32bitvedic and square
- 32 bit vedic multiplier documentation
jeas_reversable-vedic-multiplier
- reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output