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D触发器的设计
- D触发器的设计 主要用在时序电路中。 所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
verilog
- verilog原理与应用 作者：Michael D. Ciletti
带同步清0、同步置1 的D 触发器
- 带同步清0、同步置1 的D 触发器, Verilog HDL 源码
A/D转换芯片TLC2543的verilog编程
- A/D转换芯片TLC2543的verilog编程，根据TLC5243的datasheet编写，程序简单，结构清晰，可以借鉴应用-A/D converter chip TLC2543 the verilog programming
TRDB_DC2
- DE1/DE2CCD摄像头Verilog源代码。-DE1/DE2CCD camera Verilog source code.
max197
- verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
AD9708
- AD9708是高速AD转换芯片，采用VHDL实现10MSPS高速AD数据采集-AD9708 is high speed a/d conversion chip,10MSPS,using VHDL
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
Verilog DHL教程
- Verilog DHL教程-Verilog DHL course
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
D_BLAST44
- MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
DDS
- 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
dff_clk
- 简单的D触发器的Verilog描述及，仿真波形-A simple D flip-flop in Verilog descr iption and simulation waveforms
74hc74
- 带使能和清零端的D触发器，Verilog实现，有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
D_latch
- actel fpga Verilog D锁存器-actel fpga Verilog D latch
Advanced-Digital-Design-with-the-Verilog-HDL-CODE.
- 《Verilog HDL高级数字系统设计》（Michael D. Ciletti著） Verilog HDL源代码-" Verilog HDL Advanced Digital System Design" (Michael D. Ciletti a) Verilog HDL source code
verilog-d-filp-flop
- Verilog code of D-Flip Flop
D
- FPGA VERILOG实现 D触发器 -FPGA VERILOG D flip-flop
Advanced Digital Design with the Verilog HDL
- Advanced Digital Design with the Verilog HDL (M.D.Cilett)