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verilog
- 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
freqm
- a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
16bit_display8bitLED
- Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. In
7-segment
- VHDL Design of BCD to 7-segment decoder using PROM
segment
- 7 segment display using verilog interfacing fpga and 7 segment display
demtang09
- the proramme is created to be examble to leran verilog programming. it s porpuse is crease the number is 7-segment from 0 to 9.
dem4bit_hienthi
- the verilog source code for being an examble to counts 4-bit number and display in 7-segment.
seven_seg
- Verilog, 7segment, ISE
paobiao
- 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
chengfaqi.doc
- 设计一个两个5位数相乘的乘法器。用发光二极管显示输入数值，用7段显示器显示结果。乘数和被乘数分两次输入(verilog语言实现)-Design a multiplier of two 5-digit multiplication. Enter the value with the light-emitting diode display, with 7-segment display shows the results. Multiplier and the multiplicand input
digital-tube
- 实现开发板上的数码管静态循环显示0~F。通过这个实验，掌握采用Verilog HDL语言编程实现7段数码管显示译码器的方法。-The digital realization of the development board cycling static display 0 ~ F. Through this experiment, using Verilog HDL language to master programming 7-segment display decoder method
LED_7seg
- FPGA的7段数码管程序，用verilog编写，很好的程序，不要错过啊-The 7-segment FPGA program written with verilog, very good program, do not miss ah
7duanshumaguandejingtaixianshi
- 采用Verilog语言编写实现7段数码管的静态显示，经过CPLD开发板验证，程序正确-Verilog language used to achieve a static 7-segment display, after a CPLD development board verification, the program correctly
dianzimimasuo
- 采用verilog设计，7段数码管进行输入的显示，在DE-2平台上进行密码锁的实现。-Using verilog design, 7-segment LED display for input in the DE-2 platform on the lock implementation.
hex2led
- 在quantusII环境下采用verilog HDL语言编辑的7段译码器HEX2LED设计 -In quantusII environment using verilog HDL language editors design 7-segment decoder HEX2LED
decoder_bcd7seg
- Basic 7-segment decoder for Verilog
UART_RS232(verilog)
- /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作
7duanyimaguan-Verilog-HDL
- 7段译码管的Verilog HDL程序，希望对大家有用-7 segment decoder tube Verilog HDL procedures
segment
- 基于verilog xilinx spartan 的7段管显示-7-segment tube display based on verilog xilinx spartan
Verilog源代码
- 多种基本功能的Verilog代码实现，包括多路选择器，二进制到BCD码转换，二进制到格雷码转换，7段译码器，8位数据锁存器，移位寄存器等等多种功能。(Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit dat