搜索资源列表
Receiver
- 基于802.11a的OFDM基带硬件设计的verilog代码，在Xilinx ISE环境下实现-The OFDM-based 802.11a baseband hardware design of the verilog code, in the Xilinx ISE environment to achieve
Channel_Equalizer
- 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language
Sampling_Frequency_Synchronization
- 802.11a接收机的采样频率同步源码，verilog语言的-802.11a receiver sampling frequency synchronization source, verilog language
DATA_scramble
- 扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation
clock_generator
- 802.11a时钟产生、分频模块，verilog源码-802.11a clock generator, frequency module, verilog source
Frame_Detection
- OFDM系统的帧检测模块，根据802.11a标准，利用前导的相关性进行的设计，综合仿真及在线调试已通过。-Ofdm frame detection module is very important and verilog difficult to realize in OFDM system.
short_generator
- OFDM的短序列verilog语言，802.11a的标准-OFDM short sequence verilog language, 802.11a standard
80211_Transmitter_VerilogHDL
- 802.11a Transmitter implementation Using Verilog
RECEIVER
- 此程序为基于OFDM的802.11a的接收端的VERILOG代码，包含所有模块。-This program is VERILOG code receiving end 802.11a OFDM-based, including all modules.
TRANSMITTER
- 此程序为基于OFDM的802.11a的发送端的VERILOG程序，包含所有模块。-This program is VERILOG program sender 802.11a OFDM-based, including all modules.
802.11a PHY 代码
- 802.11a 物理层代码，采用verilog编写FPGA设计