搜索资源列表
OVL
- OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证-OVL- assertion-based verification of Verilog Verilog digital system design: RTL synthesis, test and verification platform
S3E_AnalogIO
- it is a analog i/o interface written in verilog .it will work on spartan 3 xilini devices.
BasicRSA_latest.tar
- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman i
DMA_8237A
- 经典DMA控制器8237A的VHDL设计，对设计DMA控制器有很高的参考价值。-Classic DMA controller 8237A of the VHDL design, the design of the DMA controller has a high reference value.
vmachine
- Verilog code for vending machine.. Descr iption: Vending machine ll take two quarters and distribute one of the two flavors of juice(apple or orange). Inputs: • Q : A quarter has been inserted. • O : orange juice button is press
t4
- Explain the very good teaching Ve failed to translate miller overall lack of success of verilog language miller decoding Miller verilog language decoder o 4 Multiplier VHDL language design DRAM Controller verilog file
XILINX
- Verilog汇编很牛叉 O(∩_∩)O哈哈哈~-Verilog
source
- 包含了verilog hdl实验的很多源代码\(^o^)/~-Contains a verilog hdl a lot of experimental code \ (^ o ^)/~
Writing-Testbenches-using-System-Verilog.tar
- Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from
86verilog
- 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith t
dw8051-used-in-FPGA
- 自己下载的dw8051核，并在atlys fpga开发板上运行成功。其中rom和ram都已经生成，4个并行I/O口也有。编程语言是verilog。另外，还有hex转in文件的小软件，以及Uedit这个文本编辑器，它是用来给dw8051的rom载入程序的。-The the dw8051 nuclear, download and run atlys fpga development board. Rom and ram have been generated, there are four par
contador-caso-especial-y-procedimientos
- contadores y ejemplos de diseñ o en verilog
counter
- 计算器的verilog语言程序代码。能实现加、减、乘、除运算。-verilog language of counter。it can achiev plus o, minus, multiplication and addition operations
ex1_clkdiv
- 这个实验可以说是verilog入门最基础的实验了，我们不做太多的理论分析，实践是硬道理。 当CPLD的I/O（ FM）为低电平时，三极管导通， 蜂鸣器发声。-This experiment can be said to be the most basic experiments verilog entry, and we do not do a lot of theoretical analysis, practice is the last word. When the CPLD' s
user_encoded_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
safe_state_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
verilog-code-ch-04
- veri lo g ve ri l o g
Digital_clock
- 教程 基于FPGA的智能闹钟，控制NOKIA5110(Intelligent alarm clock based on FPGA, control N O K I A 5110)
raw
- Implementation of Amstrad gate array 40010 o verilog
IIC_Verilog
- I2C接口代码，v e r i l o g(The code of I2C interface, verilog HDL)