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pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
ALU
- 算术逻辑部件的verilog代码，它能够实现半加器、全加器、比较、按位与、按位或、按位异或、加一、减一的操作-Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation
compare
- 一个用verilog写的基本的比较器，其中带了一些其他的电路，也是用verilog编的，希望对读者有用。-Use verilog to write a basic comparator, which brought a number of other circuits, but also with the verilog code, and I hope useful to readers.
compare
- Verilog实现的比较器，内含全部源码。-Comparators implemented Verilog, containing all the source code.
cookbook
- 用于verilog入门的小程序，包括各种crc,compare等常用硬件电路的描述-verilog cookbook，including several verilog code of crc，compare circuit etc.
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
datacompare
- 采用verilog语言来进行数据比较器 附带仿真波形-Verilog language used to compare data with simulation waveform control
Verilog
- verilog参考例子，有简单的compare，有时序电路，源代码和仿真-examples using verilog
multiplier
- 几种verilog乘法器的代码，用于比较不同乘法器特点-Several multiplier verilog code, used to compare the different characteristics of the multiplier
compare
- 比较器，四位的比较器，verilog的语言编写的，可以用-The comparator, the comparator four, Verilog language, can be used
compare
- verilog两个数的比较，由加法器改编而来-verilog comparison
compare
- 数值比较器的设计，课堂作业随堂检查，verilog语言设计，开发工具是quartus II7.0以上版本，测试仿真脚本也有-Numerical comparison of the design, classwork class check the Verilog language design, development tools is quartus II7.0 above test simulation scr ipt
compare
- 三个数的比较，输出最大值，Verilog实现，已经建立modelsim工程，可以直接观看波形， Verilog 最大值，fpga-Verilog max value
ALU
- verilog编写，八位ALU，加减与或比较-verilog prepared eight ALU, subtract, or compare with
alu
- 32位alu模块实现加减法、逻辑运算、移位、比较和置高位立即数等功能。verilog实现。-32-bit alu module achieves functions like addition and subtraction, logical operations, shift, compare, and set a high immediate number by verilog
t2_manchester_coder
- Manchester 编码器的Verilog与VHDL实现，并分别采用moore和mealy机对其进行描述，比较了两种实现方法的不同。并且每种情况都给出了测试脚本，希望对您有用。-Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And
tlc549adc
- 使用verilog编写的利用状态机实现对TLC549的采样控制，实验时可调节电位器，改变ADC 的模拟量输入值，数据采集读取后在数码管上显示。可以自己用万用表测一下输入电压， 然后与读取到的数据比较一下。-Use verilog prepared using the state machine to achieve the TLC549 sampling control, adjustable potentiometer experiment, change ADC The anal
compare
- 用Verilog HDL编写的简单的比较器-A simple comparator programmed by Verilog Hdl
compare
- 用verilog实现文件输入的比较器，如果同一时间输入的数据相同则输出高电平，否则输出低电平，达到比对的效果。-Use verilog implementation file input comparator, if the input data at the same time the same output high level, otherwise the output low level, to achieve the effect of alignment.
FPGAcode
- verilog HDL语言编程实现比较、分频、除法、阻塞与非阻塞语句的源文件和test文件-compare, division,half_clock,block and unblock