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FPGA_DDR_SDRAMverilog
- 基于Xilinx FPGA的DDRSDRAM的Verilog控制代码，使用的FPGA为Virtex-4，实现对DDRSDRAM的简单控制（对一系列地址的写入和读取）。-Xilinx FPGA-based DDRSDRAM the control of the Verilog code, the use of the FPGA for the Virtex-4, to achieve a simple DDRSDRAM control (on a series of addresses to wr
DDS
- 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
dd
- ip megacore verilog 使用代码-ip megacore verilog using code
dd
- 八位全加器的源代码，用verilog编写，没有附带测试程序-eight summury
dd
- Digital Delay using Verilog (The program is wrrong I ll upload the right one soon)
DD
- it is about the verilog coding. this book will help you guys