搜索资源列表
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
USB2.0IP.rar
- 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档,Complete Verilog language developed by USB2.0 IP core source code, including documentation
fft_verilog.rar
- FFT IP core 源码 状态控制机,FFT IP core
VERILOG-USB2.0IP-core
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
FFT_verilog
- verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
ARMcore
- 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
10100MIP
- 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码，可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
photo_verilog
- verilog开发的电子相册系统，是基于Altera的FPGA芯片和IP核的设计！-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
cyc2_cmon_080805
- Verilog 8051 IP Core for Cyclone -Verilog 8051 IP Core for Cyclone II
i2c_master_slave_core
- I2C master/slave IP core
tripledes
- 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
aes_core
- aes_core verified verilog ip core-aes_core verified verilog ip core
arm7verilog
- ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
sd_slave_device
- verilog source code for SD card SLAVE DEVICE IP-Core
pipelined_fft_64
- 利用IP Core编写的Verilog程序，实现FFT变换，希望对大家有帮助。-Written using Verilog IP Core procedures to achieve FFT transformation, we want to help.
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
ethernet10-100M-IP-core
- 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
verilog-ip-core
- verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems