搜索资源列表
lab.rar
- verilog hdl经典例程，全部调试通过,verilogHdl example，all can be used
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
Log_Shifter_Gate_Level_Design
- Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
VerilogLabSource
- Verilog Lab Source Codes
Verilog+lab+3+-+HTN+lab+2
- a lab by vhdl, let discover and enjoy it now
86verilog
- 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith t
lab
- verilog语言设计同步加法器，异步减法器，16位计数器-adder verilog language design synchronous, asynchronous subtractor, 16-bit counter
verilog-programs
- These are first programs of my asic and fpgas lab.This folder contains simple half adder and its test bench using verilog language.Then it also contains 4 to 1 mux using two 2 to 1 muxes.Then its also has its test bench to check the code.These progra
eda-verilog-report
- EDA的实验报告，有六个入门级实验，写得比较详细，方便大家学习，传阅-EDA lab reports, there are six entry-level experiment, written in more detail, to facilitate learning, circulated
lab1_Verilog
- verilog lab 是一个verilog 的实验文件，是初学者的学习材料。-verilog verilog lab is an experiment file, a beginner' s learning materials.
computer-architecture-lab
- this document explain the majors of VERILOG language in a very efficient and briefly manner.this is very useful to learn about hardware design and implementing them by FPGAs.
m.e-lab
- vhdl verilog code for alu operation pll,biy sliced processor
LAB-1
- 用组合电路实现的ROM,编程环境为QUARTUS II，verilog编写的例程。-The combinational circuit ROM programming environment QUARTUS II, verilog written routines.
LAB-2
- 用FPGA实现对VGA的控制，没有用到niosII,只是用硬件描述语言verilog。整个工程。-With FPGA VGA control is not used niosII, just verilog hardware descr iption language. The entire project.
LAB-15
- FPGA实现对电梯的设计，verilog实现的。-FPGA implementation of the design of the elevator, verilog achieved.
LAB-16
- 用FPGA实现的性线反馈移位寄存器（LFSR）设计。整个工程在quartusII环境下，用verilog编程。-FPGA implementation of the line feedback shift register (LFSR) design. The whole project in verilog programming the quartusII environment.
coa lab
- lab assignmenbt in verilog
Lab1_Skeleton.tar
- adder verilog lab 1 assignment
lab0_32
- 大学生专业课的lab，用Verilog实现半加器(the necessary lab for college students to fulfill the function of half-adder)
Verilog数字VLSI设计教程（源码）
- Verilog 数字VLSI 设计教程 官方Lab(Verilog Digital VLSI Design Course Official Lab)