搜索资源列表
VerilogA_Compact_Model_Extensions
- 采用wverilog-a描述模型的主要方式-Wverilog-a descr iption of the use of the main form of model
verilog-A_library
- Complete Verilog-A library for analog blocks, like ADC, DAC, amplifiers
iverilog-0.9.2
- iverilog是verilog仿真综合工具，能够将verilog源代码编译为不同的目标文件-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format
verilog_a_modeling
- verilog-a 建模，在Cadence 中建立一个二级运放的VerilogA行为级模型，并进行建立时间等等仿真，以及对S/H电路的建模和仿真。 -verilog-a model in Cadence to create a secondary op amp VerilogA behavioral model and the simulation set-up time, etc., as well as S/H circuit modeling and simulation.
verilogA_INL_DNL
- verilogA 测试ADC的INL和DNL-test ADC INL DNL by VerilogA
veriloga
- veriloga 设计手册，包含所有语句例程，适合新手使用。-veriloga design book, full of examples.
hspice_app_manual
- 适用于集成电路领域，进行电路设计与仿真。(It is applied in the field of integrated circuits.)